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    • 1. 发明授权
    • Nonvolatile memory device, and its manufacturing method
    • 非易失存储器件及其制造方法
    • US07307879B2
    • 2007-12-11
    • US11291048
    • 2005-11-29
    • Atsushi YokoiMasao Nakano
    • Atsushi YokoiMasao Nakano
    • G11C16/04H01L29/788H01L29/792
    • G11C16/0475G11C11/5621G11C2211/5611H01L21/28273H01L27/115H01L27/11521H01L29/42328H01L29/42344H01L29/42348H01L29/66825H01L29/7887H01L29/7923
    • On a channel region enclosed by a pair of diffusion layers 13A, 13B, a first insulating layer 15, a charge accumulative layer 17, and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19, two control gate layers 21A, 21B spaced across a gap G1 are disposed in the middle of the channel width direction. The charge accumulative layer 17 has discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer 17, the charges injected depend on the writing voltage applied in control gate layers 21A, 21B and can be localized beneath the control gate layers 21A, 21B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layers 21A, 21B, so that multi-value storage in the memory cell can be realized.
    • 在由一对扩散层13A,13B,第一绝缘层15,电荷累积层17和第二绝缘层19围绕的沟道区域上依次层叠,在第二绝缘层19上, 在间隙G 1间隔开的两个控制栅极层21A,21B设置在沟道宽度方向的中间。 电荷累积层17具有离散的电荷陷阱,因此层中的电荷的移动受到限制。 在电荷累积层17中,注入的电荷取决于施加在控制栅极层21A,21B中的写入电压,并且可以位于施加写入电压的控制栅极层21A,21B的下方。 可以在控制栅极层21A,21B下方的每个电荷累积区域中控制电荷的存在或不存在,从而可以实现存储单元中的多值存储。
    • 2. 发明申请
    • Nonvolatile memory device, and its manufacturing method
    • 非易失存储器件及其制造方法
    • US20060114722A1
    • 2006-06-01
    • US11291048
    • 2005-11-29
    • Atsushi YokoiMasao Nakano
    • Atsushi YokoiMasao Nakano
    • G11C16/04
    • G11C16/0475G11C11/5621G11C2211/5611H01L21/28273H01L27/115H01L27/11521H01L29/42328H01L29/42344H01L29/42348H01L29/66825H01L29/7887H01L29/7923
    • On a channel region enclosed by a pair of diffusion layers 13A, 13B, a first insulating layer 15, a charge accumulative layer 17, and a second insulating layer 19 are stacked up in this order, and on the second insulating layer 19, two control gate layers 21A, 21B spaced across a gap G1 are disposed in the middle of the channel width direction. The charge accumulative layer 17 has discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer 17, the charges injected depend on the writing voltage applied in control gate layers 21A, 21B and can be localized beneath the control gate layers 21A, 21B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layers 21A, 21B, so that multi-value storage in the memory cell can be realized.
    • 在由一对扩散层13A,13B,第一绝缘层15,电荷累积层17和第二绝缘层19围绕的沟道区域上依次层叠,在第二绝缘层19上, 在间隙G 1间隔开的两个控制栅极层21A,21B设置在沟道宽度方向的中间。 电荷累积层17具有离散的电荷陷阱,因此层中的电荷的移动受到限制。 在电荷累积层17中,注入的电荷取决于施加在控制栅极层21A,21B中的写入电压,并且可以位于施加写入电压的控制栅极层21A,21B的下方。 可以在控制栅极层21A,21B下方的每个电荷累积区域中控制电荷的存在或不存在,从而可以实现存储单元中的多值存储。
    • 5. 发明授权
    • Storage controller and storage control method
    • 存储控制器和存储控制方法
    • US08549349B2
    • 2013-10-01
    • US13023150
    • 2011-02-08
    • Atsushi YuharaMasao NakanoTakao SatoKazunobu OhashiTakahiko Takeda
    • Atsushi YuharaMasao NakanoTakao SatoKazunobu OhashiTakahiko Takeda
    • G06F11/00
    • G06F11/2092G06F11/0724G06F11/0727G06F11/0757
    • This storage controller includes a port unit and multiple processing units for inputting and outputting data to and from a storage apparatus. The port unit sorts the data I/O requests given from a host system to the corresponding processing units according to a table pre-defining the storage apparatus or a storage area in the storage apparatus to perform data I/O processing allocated to each of the processing units. The processing unit inputs data in the corresponding storage apparatus or the corresponding storage area according to the data I/O request sorted to itself from the port unit and, upon detecting a blockage of the other processing unit due to a failure, updates the table retained in each of the port units so as to sort the storage apparatuses or the storage areas allocated to the other processing unit to the remaining unblocked processing units.
    • 该存储控制器包括端口单元和用于向存储装置输入和输出数据的多个处理单元。 端口单元根据预先定义存储装置的表或存储装置中的存储区域将从主机系统给出的数据I / O请求分类到相应的处理单元,以执行分配给每个处理单元的数据I / O处理 处理单位。 处理单元根据从端口单元自身分配的数据I / O请求在对应的存储装置或对应的存储区域中输入数据,并且在检测到由于故障导致的其他处理单元的阻塞时更新保留的表 在每个端口单元中,将分配给其他处理单元的存储装置或存储区域分配给剩余的未阻塞处理单元。
    • 6. 发明申请
    • STORAGE CONTROLLER AND STORAGE CONTROL METHOD
    • 存储控制器和存储控制方法
    • US20110126058A1
    • 2011-05-26
    • US13023150
    • 2011-02-08
    • Atsushi YuharaMasao NakanoTakao SatoKazunobu OhashiTakahiko Takeda
    • Atsushi YuharaMasao NakanoTakao SatoKazunobu OhashiTakahiko Takeda
    • G06F11/16
    • G06F11/2092G06F11/0724G06F11/0727G06F11/0757
    • This storage controller includes a port unit and multiple processing units for inputting and outputting data to and from a storage apparatus. The port unit sorts the data I/O requests given from a host system to the corresponding processing units according to a table pre-defining the storage apparatus or a storage area in the storage apparatus to perform data I/O processing allocated to each of the processing units. The processing unit inputs data in the corresponding storage apparatus or the corresponding storage area according to the data I/O request sorted to itself from the port unit and, upon detecting a blockage of the other processing unit due to a failure, updates the table retained in each of the port units so as to sort the storage apparatuses or the storage areas allocated to the other processing unit to the remaining unblocked processing units.
    • 该存储控制器包括端口单元和用于向存储装置输入和输出数据的多个处理单元。 端口单元根据预先定义存储装置的表或存储装置中的存储区域将从主机系统给出的数据I / O请求分类到相应的处理单元,以执行分配给每个处理单元的数据I / O处理 处理单位。 处理单元根据从端口单元自身分配的数据I / O请求在对应的存储装置或对应的存储区域中输入数据,并且在检测到由于故障导致的其他处理单元的阻塞时更新保留的表 在每个端口单元中,将分配给其他处理单元的存储装置或存储区域分配给剩余的未阻塞处理单元。
    • 9. 发明申请
    • Radar apparatus
    • 雷达装置
    • US20060028375A1
    • 2006-02-09
    • US11189732
    • 2005-07-27
    • Kanako HondaMasao Nakano
    • Kanako HondaMasao Nakano
    • G01S13/42
    • G01S13/4454G01S13/584
    • In an FM-CW radar apparatus which determines the azimuth to a target by a phase monopulse technique, an abnormal value resulting from the presence of multiple targets is detected. Three receiving antennas are arranged at spacings of 5λ/4 and 6λ/4, respectively, and it is determined whether the difference between the azimuth obtained from the combination of the receiving antennas spaced 5λ/4 apart and the azimuth obtained from the combination of the receiving antennas spaced 6λ/4 apart is smaller than a predetermined value or not; when the condition has been satisfied n times in succession, it is determined that the detected value is normal. On the other hand, if the condition has not been satisfied n times in succession, or if the difference is not smaller than the predetermined value, it is determined that the detected value is an abnormal value resulting from the presence of multiple targets.
    • 在通过相位单脉冲技术确定目标的方位角的FM-CW雷达装置中,检测到由多个目标的存在引起的异常值。 三个接收天线分别以5lambda / 4和6λ/ 4的间隔排列,并且确定从接收天线的组合获得的方位角之间的间隔为5λ/ 4的距离和从 间隔6λ/ 4的接收天线小于预定值; 当条件已经连续满足n次时,确定检测值正常。 另一方面,如果条件未连续满足n次,或者如果差值不小于预定值,则确定检测值是由于存在多个目标而导致的异常值。