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    • 3. 发明授权
      US5734881A Detecting short branches in a prefetch buffer using target location information in a branch target cache 失效
    • Detecting short branches in a prefetch buffer using target location information in a branch target cache
    • 使用分支目标缓存中的目标位置信息检测预取缓冲区中的短分支
    • US5734881A
    • 1998-03-31
    • US572773
    • 1995-12-15
    • Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
    • Christopher E. White , Antone L. Fourcroy , Mark W. McDermott
    • G06F9/38
    • G06F9/3812 , G06F9/30054 , G06F9/3806 , G06F9/3814
    • A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch buffer, thereby avoiding issuing a prefetch request to retrieve the target. The branch unit includes a branch target cache (BTC) in which each entry stores, in addition to target address information for prefetching a prefetch block of instruction bytes containing a target instruction, a prefetch block location field--when this field is valid, it provides the location of the target instruction for a short branch within a prefetch block that is already in the prefetch buffer. In response to a branch that hits in the BTC, if the associated prefetch block location field is valid, the prefetch unit is able to begin transferring instruction bytes for the target instruction without issuing a prefetch request for the prefetch block containing the target instruction. The exemplary prefetch unit uses a three-block prefetch buffer each storing a 16 byte (cache line) prefetch block--the three prefetch buffers are logically allocated for the current, next, and previous prefetch blocks, and the target of a short branch may be either forward or backward of the branch, and may reside in the same prefetch buffer as the branch (which logically will be current) or in a contiguous prefetch buffer (logically next or previous). Avoiding prefetch requests in the case of short branches reduces contention for cache access and associated bus traffic.
    • 流水线x86处理器包括预取单元（预取缓冲器）和协作以检测分支目标（指定为短分支）何时已经在预取缓冲器中的分支单元，从而避免发出预取请求以检索目标。 分支单元包括分支目标高速缓存（BTC），除了用于预取包含目标指令的指令字节的预取块的目标地址信息之外，每个条目还存储预取块位置字段 - 当该字段有效时，其提供 在预取块中已经在预取缓冲器中的短分支的目标指令的位置。 响应于在BTC中击中的分支，如果相关联的预取块位置字段有效，则预取单元能够开始传送用于目标指令的指令字节，而不对包含目标指令的预取块发出预取请求。 示例性预取单元使用三块预取缓冲器，每个存储16字节（高速缓存线）预取块 - 三个预取缓冲器在逻辑上分配给当前，下一个和先前的预取块，并且短分支的目标可以是 分支的前向或后向，并且可以驻留在与分支（逻辑上将是当前）相同的预取缓冲器中，或者在连续的预取缓冲器（逻辑上是下一个或前一个）中。 在短分支的情况下避免预取请求减少了缓存访问和相关总线流量的争用。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US4931748A Integrated circuit with clock generator 失效
    • Integrated circuit with clock generator
    • 集成电路与时钟发生器
    • US4931748A
    • 1990-06-05
    • US364510
    • 1989-06-09
    • Mark W. McDermott , Antone L. Fourcroy
    • Mark W. McDermott , Antone L. Fourcroy
    • G01R29/027 , G06F1/04 , H03L7/14
    • H03L7/14 , G01R29/0273 , G06F1/04
    • A microprocessor or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.
    • 包括取决于外部提供的参考信号的时钟发生器电路的微处理器或其他集成电路包括检测该外部提供的参考信号的损耗并产生替代时钟信号的能力，尽管参考的丢失。 在特定实施例中，时钟发生器包括锁相环频率合成器，其通常依赖于外部晶体振荡器用于其参考频率信号。 发生器包括用于检测晶体信号中的异常并将频率合成器的压控振荡器切换到内部产生的参考电压的电路。 在特定实施例中，时钟发生器还能够响应于参考信号的丢失而产生复位信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5860105A NDIRTY cache line lookahead 失效
    • NDIRTY cache line lookahead
    • NDIRTY高速缓存行前瞻
    • US5860105A
    • 1999-01-12
    • US557977
    • 1995-11-13
    • Mark W. McDermott , Robert W. French , Antone L. Fourcroy , Mark E. Burchfield , Xiaoli Y. Mendyke
    • Mark W. McDermott , Robert W. French , Antone L. Fourcroy , Mark E. Burchfield , Xiaoli Y. Mendyke
    • G06F12/08 , G06F12/00
    • G06F12/0804 , G06F12/0891
    • An NDIRTY cache line lookahead technique is used to expedite cache flush and export operations by providing a mechanism to avoid scanning at least some cache lines that do not contain dirty data (and therefore will not have to be exported). The exemplary cache organization uses one-line lookahead where each cache line but the last has associated with it an NDIRTY bit that indicates whether the next cache line contains dirty data. For cache flush and export operations, when a cache line (N) is read to check for dirty data that must be exported, the NDIRTY bit for that cache line is also tested to determine whether the next cache line (N+1) contains dirty data--if the NDIRTY bit is clear, indicating that the next cache line is clean, then that line is skipped and the scan proceeds with the line after that (N+2). This exemplary one-line lookahead implementation is readily extendible to N-line lookahead. The cache line lookahead technique reduces the number of cache line accesses required during flush/export operations, with the attendant advantages of reduced flush/export penalty cycles and power, thereby improving overall system performance.
    • NDIRTY高速缓存行前瞻技术用于通过提供一种机制来避免扫描至少一些不包含脏数据的缓存行（因此不必被导出）来加速缓存刷新和导出操作。 示例性高速缓存组织使用单行前瞻，其中每个高速缓存行但最后一行与其相关联的NDIRTY位指示下一个高速缓存行是否包含脏数据。 对于缓存刷新和导出操作，当读取高速缓存行（N）以检查必须导出的脏数据时，还会测试该高速缓存行的NDIRTY位，以确定下一个高速缓存行（N + 1）是否包含脏 数据 - 如果NDIRTY位清除，表示下一个高速缓存行是干净的，那么该行被跳过，扫描将继续进行（N + 2）之后的行。 这种示例性的单行前瞻实现可以容易地扩展到N行前瞻。 高速缓存行前瞻技术减少了刷新/导出操作期间所需的高速缓存行访问次数，同时具有降低冲洗/导出惩罚周期和功率的优点，从而提高了整体系统性能。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5361392A Digital computing system with low power mode and special bus cycle therefor 失效
    • Digital computing system with low power mode and special bus cycle therefor
    • 具有低功耗模式和特殊总线周期的数字计算系统
    • US5361392A
    • 1994-11-01
    • US033992
    • 1993-03-19
    • Antone L. Fourcroy , Mark W. McDermott , John P. Dunn , Bradley G. Burgess
    • Antone L. Fourcroy , Mark W. McDermott , John P. Dunn , Bradley G. Burgess
    • G06F1/04 , G06F1/32 , G06F15/78 , G06F9/30 , G06F9/46 , G06F11/20 , G06F13/24
    • G06F9/30083 , G06F1/3203 , G06F9/30167
    • A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An integrated circuit microcomputer enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system within the microcomputer. This subsystem then shuts down the clock signals to the remainder of the microcomputer, leaving only this sub-system active. The active sub-system performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode. Only if the priority level of an interrupt is sufficiently high are the clock signals resumed, thus terminating the low power mode.
    • 具有低功率操作模式的数字计算系统包括用于在进入低功率模式之前通信的信息，该信息确定哪些事件将能够导致低功率模式的终止。 响应于执行LPSTOP指令，集成电路微计算机进入低功率模式。 只有重置事件和具有足够高的优先级才能通过中断掩码的中断事件才能导致低功率模式的终止。 LPSTOP指令将立即数据加载到状态寄存器中，复位中断屏蔽位。 然后通过专用总线周期将中断屏蔽写入微机内的子系统中的中断屏蔽寄存器。 该子系统然后将时钟信号关闭到微计算机的其余部分，只剩下这个子系统。 在低功耗模式下，有源子系统对接收到的中断请求的优先级进行中断屏蔽的比较。 只有当中断的优先级足够高时，恢复时钟信号，从而终止低功耗模式。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5448744A Integrated circuit microprocessor with programmable chip select logic 失效
    • Integrated circuit microprocessor with programmable chip select logic
    • 具有可编程芯片选择逻辑的集成电路微处理器
    • US5448744A
    • 1995-09-05
    • US432423
    • 1989-11-06
    • James B. Eifert , John J. Vaglica , James C. Smallwood , Mark W. McDermott , Hiroyuki Sugiyama , William P. LaViolette , Bradley G. Burgess
    • James B. Eifert , John J. Vaglica , James C. Smallwood , Mark W. McDermott , Hiroyuki Sugiyama , William P. LaViolette , Bradley G. Burgess
    • G06F9/38 , G06F9/22 , G06F13/10
    • G06F9/3877
    • An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.
    • 集成电路微处理器具有板载可编程芯片选择逻辑。 几个芯片选择输出中的每一个可以通过一个或多个控制寄存器位字段单独编程。 例如，每个芯片选择在起始地址和块大小均可编程的地址范围内被断言用于总线周期。 此外，每个芯片选择都可以被编程为仅在读周期有效，仅在写周期或读周期和写周期。 只有在确认中断与该芯片选择相同的优先级时，每个芯片选择才能在中断确认周期内被编程为有效。 此外，每个芯片选择的断言的定时可编程为与总线周期的地址选通或数据选通一致。 芯片选择逻辑被设计为使得其被配置为在复位之后由处理器运行的第一总线周期期间产生有效芯片选择信号而退出复位。 该芯片选择适用于选择引导ROM，然后可以重新编程以供其他使用。 芯片选择逻辑能够通过断言适当的周期终止信号来支持逐周期动态总线大小调整。 芯片选择逻辑还可以将可编程的等待状态数插入总线周期以适应慢速外设，或者可能导致总线周期的快速终止，从而提高快速外设的利用率。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5592107A Configurable NAND/NOR element 失效
    • Configurable NAND/NOR element
    • 可配置NAND / NOR元件
    • US5592107A
    • 1997-01-07
    • US497491
    • 1995-06-30
    • Mark W. McDermott , John E. Turner
    • Mark W. McDermott , John E. Turner
    • H03K19/173 , H03K19/0948
    • H03K19/1736
    • A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.
    • 在示例性实施例中，在包括在处理器或其他集成电路中的备用阵列阵列中使用可配置NAND / NOR逻辑元件。 NAND / NOR逻辑元件（图3,50）可通过C（配置）输入（可以被金属可配置为被断言或无效）配置为NAND或NOR门。 C输入控制p沟道晶体管和n沟道晶体管。 取决于C输入是否被断言或断言，相应的内部节点被短路以实现所选择的配置。 具体来说，解锁C提供NAND配置，而断言C提供NOR配置。 在替代实施例中，NAND / NOR逻辑元件可用于全加器以提供进位输出。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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