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1. 发明授权

US08812826B2 Processor testing 有权
标题翻译：处理器测试
公开(公告)号：US08812826B2
公开(公告)日：2014-08-19
申请号：US12908370
申请日：2010-10-20
申请人： Abhishek Bansal , Nitin Gupta , Brad L. Herold , Jayakumar N Sankarannair
发明人： Abhishek Bansal , Nitin Gupta , Brad L. Herold , Jayakumar N Sankarannair
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/3005 , G06F9/3804 , G06F11/2236 , G06F11/28
摘要： In one implementation, processor testing may include the ability to randomly generate a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. Processor testing may also include the ability to randomly generate a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. Processor testing may additionally include the ability to generate a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
摘要翻译：在一个实现中，处理器测试可以包括随机生成指令集的第一部分的第一多个分支指令的能力，第一部分中的每个分支指令分支到指令集的第二部分中的相应指令，分支指令的分支到相应的指令以顺序的方式排列。处理器测试还可以包括随机生成指令集的第二部分的第二多个分支指令的能力，第二部分中的每个分支指令分支到指令集的第一部分中的相应指令，相应指令的分支指令按顺序排列。处理器测试可以另外包括在执行期间遇到每个分支指令时产生多个指令来增加计数器的能力。

2. 发明申请

US20120102302A1 PROCESSOR TESTING 有权
公开(公告)号：US20120102302A1
公开(公告)日：2012-04-26
申请号：US12908370
申请日：2010-10-20
申请人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/3005 , G06F9/3804 , G06F11/2236 , G06F11/28
摘要： Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.

3. 发明授权

US08914622B2 Processor testing 有权
标题翻译：处理器测试
公开(公告)号：US08914622B2
公开(公告)日：2014-12-16
申请号：US13460413
申请日：2012-04-30
申请人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/32 , G06F11/22 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30058 , G06F9/3005 , G06F9/3804 , G06F11/2236 , G06F11/28
摘要： Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
摘要翻译：处理器可以根据各种实现来测试。在一般的实现中，用于处理器测试的过程可以包括为指令集的第一部分随机生成第一多个分支指令，第一部分中的每个分支指令分支到指令集的第二部分中的相应指令，分支指令的分支到相应的指令以顺序的方式排列。该过程还可以包括随机生成用于指令集的第二部分的第二多个分支指令，第二部分中的每个分支指令分支到指令集的第一部分中的相应指令，分支指令分支到相应的指令按顺序排列。该过程可以另外包括在执行期间遇到每个分支指令时产生多个指令来增加计数器。

4. 发明申请

US20120216023A1 PROCESSOR TESTING 有权
标题翻译：处理器测试
公开(公告)号：US20120216023A1
公开(公告)日：2012-08-23
申请号：US13460413
申请日：2012-04-30
申请人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
发明人： Abhishek Bansal , Nitin P. Gupta , Brad L. Herold , Jayakumar N. Sankarannair
IPC分类号： G06F9/30
CPC分类号： G06F9/30058 , G06F9/3005 , G06F9/3804 , G06F11/2236 , G06F11/28
摘要： Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in the first portion branching to a respective instruction in a second portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may also include randomly generating a second plurality of branch instructions for the second portion of the instruction set, each branch instruction in the second portion branching to a respective instruction in the first portion of the instruction set, the branching of the branch instructions to the respective instructions being arranged in a sequential manner. The process may additionally include generating a plurality of instructions to increment a counter when each branch instruction is encountered during execution.
摘要翻译：处理器可以根据各种实现来测试。在一般的实现中，用于处理器测试的过程可以包括为指令集的第一部分随机生成第一多个分支指令，第一部分中的每个分支指令分支到指令集的第二部分中的相应指令，分支指令的分支到相应的指令以顺序的方式排列。该过程还可以包括随机生成用于指令集的第二部分的第二多个分支指令，第二部分中的每个分支指令分支到指令集的第一部分中的相应指令，分支指令分支到相应的指令按顺序排列。该过程可以另外包括在执行期间遇到每个分支指令时产生多个指令来增加计数器。

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