会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明申请
    • ANTI-THEFT SYSTEM USING RFID TAGS
    • 使用RFID标签的防盗系统
    • US20130135106A1
    • 2013-05-30
    • US13596037
    • 2012-08-27
    • HSIN-PEI CHANGZONG-YUAN SUNDA-HUA XIAO
    • HSIN-PEI CHANGZONG-YUAN SUNDA-HUA XIAO
    • G08B13/14
    • G08B13/149B65D2211/00
    • A detection unit positioned on a package includes a magnet, a first magnetic switch, a second magnetic switch, a processor, and a clock. The first magnetic switch outputs a first control signal or a second control signal according to magnetic flux density of the magnet. The second magnetic switch outputs a third control signal or a fourth control signal according to the magnetic flux density of the magnet. The first control signal is the same as the third control signal; the second control signal is the same as the fourth control signal. When the processor receives the first control signal and the third control signal at the same time, the processor reads a first real-time clock (RTC) signal from the clock. When the processor receives the second control signal and the fourth control signal at the same time, the processor reads a second RTC signal from the clock.
    • 定位在包装上的检测单元包括磁体,第一磁性开关,第二磁性开关,处理器和时钟。 第一磁性开关根据磁体的磁通密度输出第一控制信号或第二控制信号。 第二磁性开关根据磁体的磁通密度输出第三控制信号或第四控制信号。 第一控制信号与第三控制信号相同; 第二控制信号与第四控制信号相同。 当处理器同时接收第一控制信号和第三控制信号时,处理器从时钟读取第一实时时钟(RTC)信号。 当处理器同时接收第二控制信号和第四控制信号时,处理器从时钟读出第二RTC信号。
    • 8. 发明授权
    • Configurable hierarchical comma-free reed-solomon decoding circuit and method thereof
    • 可配置的分层无间断芦苇解码电路及其方法
    • US08166377B2
    • 2012-04-24
    • US12423897
    • 2009-04-15
    • Yuan-Sun ChuYi-Ren ChenChia-Ying HuangChi-Fang Li
    • Yuan-Sun ChuYi-Ren ChenChia-Ying HuangChi-Fang Li
    • H03M13/00
    • H04L1/0052H03M13/15H04L1/0057
    • The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.
    • 本发明公开了一种可配置分层无间断里德 - 索罗门解码电路及其方法。 该设计基于原始的分层并行架构,其不仅比传统解码器更快地完成解码过程,而且还利用较少的硬件来执行具有较少功耗的各种算法。 本发明的架构具有比常规收缩结构更高的解码速率,循环比为22至94.此外,本发明不需要使用ROM来存储64组码字,并且使用小于四分之一的逻辑门 的逻辑门比传统的收缩结构。 结果,本发明的电路占用的面积小于常规架构。 本发明的电路也可以针对不同的应用进行配置,因此它可以总是在各种解码要求之间找到速度和功耗之间的最佳折中。
    • 10. 发明申请
    • SYNCHRONIZER FOR COMMUNICATION DEVICE AND ACCESS POINT
    • 用于通信设备和接入点的同步器
    • US20100142506A1
    • 2010-06-10
    • US12419911
    • 2009-04-07
    • Yuan-Sun ChuTing-Huan LiYi-Ren ChenChia-Ying HuangKuo-Hua PuChi-Fang Li
    • Yuan-Sun ChuTing-Huan LiYi-Ren ChenChia-Ying HuangKuo-Hua PuChi-Fang Li
    • H04J3/06H04B7/216
    • H04W56/00H04B1/7075H04B2201/70707H04W92/10
    • The present invention discloses a synchronizer for a communication device and an access point, which is installed inside the communication device and comprises a coefficient generator generating a set of coefficient code; a parallel-to-serial converter receiving a set of input code from an access point, performing a parallel-to-serial conversion on the set of input code and outputting a result; and a coefficient element array including a plurality of coefficient elements interconnecting with each other, wherein each of the coefficient elements receives the set of input code from the parallel-to-serial converter and receives the set of coefficient code, and then performs a passive or active correlation operation on the set of input code and the set of coefficient code to output a correlation value to the access point for synchronizing signals of the communication device and the access point. The present invention has the synchronization functions of two communication systems—WCDMA and CDMA 2000, and thus can reduce the fabrication cost and increase convenience of communication.
    • 本发明公开了一种用于通信设备和接入点的同步器,其安装在通信设备内部并且包括产生一组系数代码的系数发生器; 并行 - 串行转换器,从接入点接收一组输入代码,对所述一组输入代码执行并行到串行转换并输出结果; 以及包括彼此互连的多个系数元素的系数元素阵列,其中每个系数元件从并行到串行转换器接收一组输入代码并接收该组系数代码,然后执行被动或 对输入代码集合和系数码集合进行主动相关运算,以将相关值输出到用于同步通信设备和接入点的信号的接入点。 本发明具有WCDMA和CDMA2000两种通信系统的同步功能,从而可以降低制造成本并增加通信的便利性。