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1. 发明公开

EP1312122A2 INTEGRATED TRANSISTOR DEVICES 审中-公开
标题翻译：集成器件晶体管
公开(公告)号：EP1312122A2
公开(公告)日：2003-05-21
申请号：EP01967960.4
申请日：2001-08-10
申请人： Braddock, Walter David IV
发明人： Braddock, Walter David IV
IPC分类号： H01L31/0328
CPC分类号： H01L29/802 , H01L29/513 , H01L29/517 , H01L29/7783
摘要： A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower galium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer. The refractory metal is stable on the second insulating oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22) of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers and insulators are utilized in concert with other passive circuit elements to form a integrated circuit structure.

2. 发明公开

EP0132333A3 Universal detachable mud-grips 失效
标题翻译：通用可拆卸毛绒玩具
公开(公告)号：EP0132333A3
公开(公告)日：1986-03-26
申请号：EP84304556
申请日：1984-07-04
申请人： Treadwell, Walter David
发明人： Treadwell, Walter David
IPC分类号： B60C27/20 , B60C27/16
CPC分类号： B60C27/16 , B60C27/20
摘要： A series of linked plates of sufficient length to encompass a driven wheel of a conventional road vehicle is suitably designed to reduce ground pressure and increase traction when traversing a soft or slippery surface. The linked plates are fitted to any wheel of the vehicle without recourse to jacking or to removing or replacing the wheel, and can be secured in position on each wheel by a single joining device.
摘要翻译：一系列具有足够长度的连接的板，以适于包围常规公路车辆的从动轮，适当地设计成在穿过柔软或光滑的表面时降低地面压力并增加牵引力。连接的板被安装到车辆的任何车轮上，而不需要抬头或拆卸或更换车轮，并且可以通过单个接合装置固定在每个车轮上的适当位置。

3. 发明公开

EP1315852A1 EPITAXIAL WAFER APPARATUS 审中-公开
标题翻译：外延片设备
公开(公告)号：EP1315852A1
公开(公告)日：2003-06-04
申请号：EP01956104.2
申请日：2001-08-03
申请人： Braddock, Walter David IV
发明人： Braddock, Walter David IV
IPC分类号： C30B23/02 , H01L23/31
CPC分类号： C30B23/02 , C30B29/16 , H01L29/24 , H01L29/267 , H01L29/66924 , H01L29/802 , H01L2924/0002 , Y10T117/1032 , Y10T117/108 , H01L2924/00
摘要： A system for coating the surface of compound semiconductor wafers includes providing a single-wafer epitaxial production system in a cluster-tool architecture with a loading, storage, and transfer modules, a III-V deposition chamber, and an insulator deposition chamber. The compound semiconductor wafer is placed in the loading and transfer module and the pressure is reduced to less than 5x10-10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The single wafer is then moved through the transfer module to the insulator chamber and an insulating cap layer is formed by thermally evaporating molecules, consisting essentially of gallium and oxygen, from an effusion cell using a thermal evaporation source that utilizes a metallic iridium crucible that is manufactured using the electroforming process.

4. 发明公开

EP1312122A4 INTEGRATED TRANSISTOR DEVICES 审中-公开
标题翻译：集成器件晶体管
公开(公告)号：EP1312122A4
公开(公告)日：2006-08-02
申请号：EP01967960
申请日：2001-08-10
申请人： BRADDOCK WALTER DAVID IV
发明人： BRADDOCK WALTER DAVID IV
IPC分类号： H01L21/8234 , H01L29/51 , H01L21/28 , H01L21/316 , H01L21/337 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/778 , H01L29/78 , H01L29/80
CPC分类号： H01L29/802 , H01L29/513 , H01L29/517 , H01L29/7783
摘要： A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower galium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer. The refractory metal is stable on the second insulating oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22) of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers and insulators are utilized in concert with other passive circuit elements to form a integrated circuit structure.

5. 发明公开

EP0132333A2 Universal detachable mud-grips 失效
标题翻译：通用的可拆卸泥柄
公开(公告)号：EP0132333A2
公开(公告)日：1985-01-30
申请号：EP84304556.8
申请日：1984-07-04
申请人： Treadwell, Walter David
发明人： Treadwell, Walter David
IPC分类号： B60C27/20 , B60C27/16
CPC分类号： B60C27/16 , B60C27/20
摘要： A series of linked plates of sufficient length to encompass a driven wheel of a conventional road vehicle is suitably designed to reduce ground pressure and increase traction when traversing a soft or slippery surface. The linked plates are fitted to any wheel of the vehicle without recourse to jacking or to removing or replacing the wheel, and can be secured in position on each wheel by a single joining device.
摘要翻译：一系列足够长的连接板包围传统道路车辆的从动轮，适当地设计成在穿过柔软或光滑的表面时降低地面压力并增加牵引力。链板装在车辆的任何一个车轮上，无需依靠顶起或拆卸或更换车轮，并且可通过单个连接装置固定在每个车轮上。

6. 发明公开

EP1312123A4 METAL SULFIDE SEMICONDUCTOR TRANSISTOR DEVICES 审中-公开
标题翻译：金属硫化物半导体器件晶体管
公开(公告)号：EP1312123A4
公开(公告)日：2006-08-02
申请号：EP01963936
申请日：2001-08-10
申请人： BRADDOCK WALTER DAVID IV
发明人： BRADDOCK WALTER DAVID IV
IPC分类号： H01L21/28 , H01L29/51 , H01L21/283 , H01L21/314 , H01L21/337 , H01L21/8238 , H01L27/092 , H01L29/24 , H01L29/267 , H01L29/778 , H01L29/78 , H01L29/80
CPC分类号： H01L29/802 , H01L29/24 , H01L29/267 , H01L29/513 , H01L29/517 , H01L29/66924 , H01L29/7782
摘要： A self-aligned enhancement mode metal-sulfide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide gate insulating structure. The gallium sulfide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating sulfide layer. The refractory metal is stable on the second insulating sulfide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22) of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers and insulators are utilized in concert with other passive circuit elements to form a integrated circuit structure.

7. 发明公开

EP1315852A4 EPITAXIAL WAFER APPARATUS 审中-公开
标题翻译：外延片设备
公开(公告)号：EP1315852A4
公开(公告)日：2005-02-02
申请号：EP01956104
申请日：2001-08-03
申请人： BRADDOCK WALTER DAVID IV
发明人： BRADDOCK WALTER DAVID IV
IPC分类号： H01L21/31 , C30B23/02 , H01L21/316 , H01L21/337 , H01L29/24 , H01L29/267 , H01L29/80 , H01L23/31 , C23C14/08 , C23C14/24
CPC分类号： C30B23/02 , C30B29/16 , H01L29/24 , H01L29/267 , H01L29/66924 , H01L29/802 , H01L2924/0002 , Y10T117/1032 , Y10T117/108 , H01L2924/00
摘要： A system for coating the surface of compound semiconductor wafers includes providing a single-wafer epitaxial production system in a cluster-tool architecture with a loading, storage, and transfer modules, a III-V deposition chamber, and an insulator deposition chamber. The compound semiconductor wafer is placed in the loading and transfer module and the pressure is reduced to less than 5x10-10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The single wafer is then moved through the transfer module to the insulator chamber and an insulating cap layer is formed by thermally evaporating molecules, consisting essentially of gallium and oxygen, from an effusion cell using a thermal evaporation source that utilizes a metallic iridium crucible that is manufactured using the electroforming process.

8. 发明公开

EP1312123A1 METAL SULFIDE SEMICONDUCTOR TRANSISTOR DEVICES 审中-公开
标题翻译：金属硫化物半导体器件晶体管
公开(公告)号：EP1312123A1
公开(公告)日：2003-05-21
申请号：EP01963936.8
申请日：2001-08-10
申请人： Braddock, Walter David IV
发明人： Braddock, Walter David IV
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336 , H01L29/76 , H01L29/94
CPC分类号： H01L29/802 , H01L29/24 , H01L29/267 , H01L29/513 , H01L29/517 , H01L29/66924 , H01L29/7782
摘要： A self-aligned enhancement mode metal-sulfide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide gate insulating structure. The gallium sulfide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating sulfide layer. The refractory metal is stable on the second insulating sulfide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22) of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers and insulators are utilized in concert with other passive circuit elements to form a integrated circuit structure.

9. 发明专利

AU8823901A Integrated transistor devices 未知
公开(公告)号：AU8823901A
公开(公告)日：2002-02-25
申请号：AU8823901
申请日：2001-08-10
申请人： IV WALTER DAVID WALTER
发明人： IV WALTER DAVID WALTER
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/316 , H01L21/337 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/51 , H01L29/778 , H01L29/78 , H01L29/80
摘要： A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower galium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating oxide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer. The refractory metal is stable on the second insulating oxide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22) of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers and insulators are utilized in concert with other passive circuit elements to form a integrated circuit structure.

10. 发明专利

AU8485001A Metal sulfide semiconductor transistor devices 未知
公开(公告)号：AU8485001A
公开(公告)日：2002-02-25
申请号：AU8485001
申请日：2001-08-10
申请人： IV WALTER DAVID BRADDOCK
发明人： IV WALTER DAVID BRADDOCK
IPC分类号： H01L21/28 , H01L21/283 , H01L21/314 , H01L21/337 , H01L21/8238 , H01L27/092 , H01L29/24 , H01L29/267 , H01L29/51 , H01L29/778 , H01L29/78 , H01L29/80 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336 , H01L29/76 , H01L29/94
摘要： A self-aligned enhancement mode metal-sulfide-compound semiconductor field effect transistor (10) includes a lower sulfide layer that is a mixture of Ga2S, Ga2S3, and other gallium sulfide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium sulphur layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium sulfide compound layer and the second insulating layer form a gallium sulfide gate insulating structure. The gallium sulfide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium sulphur layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating sulfide layer. A refractory metal gate electrode layer (17) is positioned on upper surface (18) of the second insulating sulfide layer. The refractory metal is stable on the second insulating sulfide layer at elevated temperature. Self-aligned source and drain areas, and source and drain contacts (19, 20) are positioned on the source and drain areas (21, 22) of the device. Multiple devices are then positioned in proximity and the appropriate interconnection metal layers and insulators are utilized in concert with other passive circuit elements to form a integrated circuit structure.

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