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1. 发明申请

US20060014393A1 Process method to facilitate silicidation 有权
标题翻译：硅化方法
公开(公告)号：US20060014393A1
公开(公告)日：2006-01-19
申请号：US10894374
申请日：2004-07-19
申请人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
发明人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
IPC分类号： H01L21/302
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/0206 , H01L21/28052 , H01L29/665
摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.
摘要翻译：本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

2. 发明申请

US20050014130A1 Label-free method for classification and characterization of cellular events 审中-公开
标题翻译：无标记的细胞事件分类和表征方法
公开(公告)号：US20050014130A1
公开(公告)日：2005-01-20
申请号：US10619820
申请日：2003-07-14
申请人： Vivian Liu , Simon Pitchford , Chris Fuller , Ed Verdonk
发明人： Vivian Liu , Simon Pitchford , Chris Fuller , Ed Verdonk
IPC分类号： G01N33/50 , C12Q1/00 , G01F1/64
CPC分类号： G01N33/502 , G01N33/5008 , G01N33/5011 , G01N33/5014 , G01N33/5041
摘要： This invention incorporates the use of bioimpedance measurements of intact cells to classify and characterize any unique global cellular event such as signal transduction from ligand/receptor interactions, cytotoxicity, apoptosis, tumor cell progression, or stem cell differentiation. Specifically, we have demonstrated that this invention can classify signal transduction pathways from G-protein coupled, tyrosine kinase, and nuclear receptors.
摘要翻译：本发明结合使用完整细胞的生物阻抗测量来分类和表征任何独特的全局细胞事件，例如从配体/受体相互作用，细胞毒性，凋亡，肿瘤细胞进展或干细胞分化的信号转导。具体来说，我们已经证明本发明可以分类来自G蛋白偶联，酪氨酸激酶和核受体的信号转导途径。

3. 发明授权

US07448395B2 Process method to facilitate silicidation 有权
标题翻译：硅化方法
公开(公告)号：US07448395B2
公开(公告)日：2008-11-11
申请号：US10894374
申请日：2004-07-19
申请人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
发明人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
IPC分类号： B08B6/00 , C25F1/00 , C25F3/30 , C25F5/00
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/0206 , H01L21/28052 , H01L29/665
摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.
摘要翻译：本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

4. 发明授权

US07112497B2 Multi-layer reducible sidewall process 有权
标题翻译：多层减薄侧壁工艺
公开(公告)号：US07112497B2
公开(公告)日：2006-09-26
申请号：US10877153
申请日：2004-06-25
申请人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
发明人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L29/517 , H01L29/6656 , H01L29/7833
摘要： The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths. The smaller second sidewall spacers facilitate compliance with design rules by allowing source and drain contacts to be formed closer to the gate structure.
摘要翻译：本发明涉及一种多层侧壁工艺（100），其有助于以允许遵守某些设计规则的方式形成晶体管，同时减轻与形成彼此靠近的晶体管的区域相关联的不利影响。具有第一宽度的第一侧壁间隔物与晶体管的栅极结构一起形成（124），以便于将源极/漏极掺杂剂远离栅极结构注入足够远，使得掺杂剂原子不可能迁移到栅极结构下方的沟道区域中。另外，该工艺为掺杂剂原子提供均匀的层以通过，以减轻跨晶片的器件特性的变化。形成侧壁间隔物的方式也允许简化自对准硅化物封堵过程。随后减小第一侧壁间隔物（132）以建立具有小于第一宽度的第二宽度的第二侧壁间隔物。较小的第二侧壁间隔件通过允许源极和漏极接触形成得更靠近栅极结构而促进了设计规则的符合性。

5. 发明申请

US20050287751A1 Multi-layer reducible sidewall process 有权
标题翻译：多层减薄侧壁工艺
公开(公告)号：US20050287751A1
公开(公告)日：2005-12-29
申请号：US10877153
申请日：2004-06-25
申请人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
发明人： Freidoon Mehrad , Vivian Liu , Amitava Chatterjee
IPC分类号： H01L21/302 , H01L21/336 , H01L21/461 , H01L29/51 , H01L29/78
CPC分类号： H01L29/6653 , H01L29/517 , H01L29/6656 , H01L29/7833
摘要： The present invention pertains to a multi-layer sidewall process (100) that facilitates forming a transistor in a manner that allows adherence to certain design rules while concurrently mitigating adverse effects associated with forming areas of transistors close to one another. First sidewall spacers having first widths are formed (124) alongside a gate structure of a transistor to facilitate implanting source/drain dopants far enough away from the gate structure so that dopant atoms are unlikely to migrate into a channel area under the gate structure. Additionally, the process provides uniform layers for dopant atoms to pass through to mitigate variations in device characteristics across a wafer. The manner of forming the sidewall spacers also allows a salicide blocking process to be simplified. The first sidewall spacers are subsequently reduced (132) to establish second sidewall spacers having second widths which are smaller than the first widths. The smaller second sidewall spacers facilitate compliance with design rules by allowing source and drain contacts to be formed closer to the gate structure.
摘要翻译：本发明涉及一种多层侧壁工艺（100），其有助于以允许遵守某些设计规则的方式形成晶体管，同时减轻与形成彼此靠近的晶体管的区域相关联的不利影响。具有第一宽度的第一侧壁间隔物与晶体管的栅极结构一起形成（124），以便于将源极/漏极掺杂剂远离栅极结构注入足够远，使得掺杂剂原子不可能迁移到栅极结构下方的沟道区域中。另外，该工艺为掺杂剂原子提供均匀的层以通过，以减轻跨晶片的器件特性的变化。形成侧壁间隔物的方式也允许简化自对准硅化物封堵过程。随后减小第一侧壁间隔物（132）以建立具有小于第一宽度的第二宽度的第二侧壁间隔物。较小的第二侧壁间隔件通过允许源极和漏极接触形成得更靠近栅极结构而促进了设计规则的符合性。

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