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    • 3. 发明授权
    • Bus system with cache snooping signals having a turnaround time between
agents driving the bus for keeping the bus from floating for an
extended period
    • 具有高速缓存监听信号的总线系统具有驾驶总线的代理之间的周转时间,以便使总线长时间不浮动
    • US5528764A
    • 1996-06-18
    • US996277
    • 1992-12-24
    • Thomas F. Heil
    • Thomas F. Heil
    • G06F12/08G06F13/364
    • G06F13/364G06F12/0831
    • A Peripheral Component Interconnect (PCI) bus for component level interconnection of processors, peripherals and memories. The PCI bus is a physical interconnect apparatus intended for use between highly integrated peripheral controller components and processor/memory systems. The PCI bus is intended as a standard interface at the component level in much the same way that ISA, EISA, or Micro Channel.TM. buses are standard interfaces at the board level. Just as ISA, EISA, and Micro Channel.TM. buses provide a common I/O board interface across different platforms and different processor generations, the PCI bus is intended to be a common I/O component interface across different platforms and different processor generations. The PCI bus lends itself to use as a main memory bus, and can be used with various cache memory techniques.
    • 外设组件互连(PCI)总线,用于处理器,外设和存储器的组件级互连。 PCI总线是用于在高度集成的外围控制器组件和处理器/存储器系统之间使用的物理互连设备。 PCI总线旨在作为组件级别的标准接口,与ISA,EISA或Micro Channel TM总线是板级标准接口的方式大致相同。 正如ISA,EISA和Micro Channel TM总线在不同平台和不同处理器世代之间提供了一个通用的I / O板接口,PCI总线旨在成为跨不同平台和不同处理器世代的通用I / O组件接口。 PCI总线本身可用作主存储器总线,并且可以用于各种高速缓冲存储器技术。
    • 8. 发明授权
    • Retry scheme for controlling transactions between two busses
    • 用于控制两台总线之间的交易的重试方案
    • US5418914A
    • 1995-05-23
    • US143393
    • 1993-10-25
    • Thomas F. HeilEdward A. McDonaldGene F. YoungCraig A. WalrathJames M. OttingerMarti D. Miller
    • Thomas F. HeilEdward A. McDonaldGene F. YoungCraig A. WalrathJames M. OttingerMarti D. Miller
    • G06F13/36G06F13/362
    • G06F13/362
    • A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource. Upon negation of the busy signal, all bus masters will be permitted to compete for ownership of the bus.
    • 一种用于优化在计算机系统中使用第一总线的重试方案,该计算机系统包括通过第一总线连接到接口电路和第二总线的多个总线主机。 接口电路包括当第二总线处于忙状态时产生忙信号的逻辑和当第二总线处于忙状态时当总线主机寻址接口电路时产生重试信号的逻辑。 每个总线主机包括用于在从接口电路接收到重试信号时接收重试信号和放弃公共总线的控制的逻辑。 总线仲裁器包括用于接收忙信号的逻辑,并且阻止任何总线主机寻求访问第二总线参与用于控制公共第一总线的仲裁,直到忙信号被否定为止。 因此,在忙信号期间,第一总线可以由不需要访问共享资源的任何总线主控器来控制。 在否定忙碌信号后,所有巴士主人将被允许竞争总线的所有权。
    • 9. 发明授权
    • Computer system configuration via test bus
    • 通过测试总线进行计算机系统配置
    • US5343478A
    • 1994-08-30
    • US800901
    • 1991-11-27
    • Larry C. JamesCarl W. KagyJeffrey F. GatesJeffrey A. HawkeyThomas F. HeilDavid L. Simpson
    • Larry C. JamesCarl W. KagyJeffrey F. GatesJeffrey A. HawkeyThomas F. HeilDavid L. Simpson
    • G01R31/3185G06F11/00G06F11/22G06F11/30G01R31/28
    • G01R31/318552G06F11/2205
    • System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough. The introduction of memory into the serial test bus permits configuration information to be stored in the modules and/or integrated circuits making up the computer system. If memory and/or other devices external to the serial test bus are included on modules or other components of the system, the time required to access these devices may exceed a default access time defined by the operating speed of the serial test bus. To ensure proper operation with such devices, a pacing or ready signal is generated such that access is delayed until the requested access can be successfully completed.
    • 系统配置,监视和控制功能在计算机系统中通过串行测试总线来执行,该串行测试总线被并入计算机系统中,用于测试用于构建系统的一个或多个模块的组件,例如集成电路。 传统的串行测试总线被修改为在计算机系统的模块上和/或在互连以构成模块的集成电路内包括寄存器电路。 这些寄存器由串行测试总线写入和读取,用于配置计算机系统,以及执行其他操作,如计算机系统中的监视和错误记录。 为了扩展可以包含在这些寄存器中的信息量,优选地,诸如EEPROM,RAM等的存储器件与寄存器相关联并且可以通过其访问。 将存储器引入串行测试总线允许将配置信息存储在构成计算机系统的模块和/或集成电路中。 如果串行测试总线外部的存储器和/或其他设备包含在系统的模块或其他组件上,则访问这些设备所需的时间可能会超过由串行测试总线的运行速度定义的默认访问时间。 为了确保使用这些设备的正常操作,生成起搏或准备就绪信号,使得访问被延迟,直到请求的访问成功完成。