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1. 发明授权

US4999603A Multi-functional basketball game monitoring unit 失效
标题翻译：多功能篮球游戏监控单元
公开(公告)号：US4999603A
公开(公告)日：1991-03-12
申请号：US435036
申请日：1989-11-13
申请人： Thomas C. Mele , Mary K. Mele , Robert C. Dyer , Margaret A. Dyer
发明人： Thomas C. Mele , Mary K. Mele , Robert C. Dyer , Margaret A. Dyer
IPC分类号： A63B69/00 , A63B71/06 , G07C1/28
CPC分类号： A63B71/06 , G07C1/28 , A63B69/0071
摘要： A multifunctional basketball game monitoring unit that allows automatic scoring taking into account foul shots, and position sensitive shots and also allows scoring of shots missed with a programmable control processing unit allowing for a great variety of differing output statistics both to visual display and to a printer and also allowing a variety of audio choices as programmed or as entered on a keyboard to the controller.
摘要翻译：一个多功能篮球游戏监控单元，允许自动计分考虑到犯规射门，并定位敏感的镜头，并且还允许通过可编程控制处理单元错过的射门得分，允许各种各样的不同的输出统计信息，包括视觉显示和打印机并且还允许在键盘上编程或输入到控制器的各种音频选择。

2. 发明授权

US5039977A Multifunctional basketball game monitoring unit 失效
标题翻译：多功能篮球游戏监控单元
公开(公告)号：US5039977A
公开(公告)日：1991-08-13
申请号：US435038
申请日：1989-11-13
申请人： Thomas C. Mele , Mary K. Mele , Robert C. Dyer , Margaret A. Dyer
发明人： Thomas C. Mele , Mary K. Mele , Robert C. Dyer , Margaret A. Dyer
IPC分类号： A63B69/00 , A63B71/06 , G07C1/28
CPC分类号： G07C1/28 , A63B71/06 , A63B69/0071
摘要： A multifunctional basketball game monitoring unit capable of sensing shots attempted and shots made in normal play and shots attempted and shots made from a spot location and further adjusting the score for the time a player remains in the air when shooting from the spot location; the unit acting to calculate, store, and display total time in play, total score, total percent of baskets made of total baskets attempted and total score shooting from the spot location for each of two backboard hoop assemblies.
摘要翻译：一种多功能篮球游戏监视单元，能够感测拍摄正常播放中的拍摄，并且从现场拍摄尝试和拍摄的照片，并且当从当地拍摄时，玩家保持在空中的时间进一步调整分数; 该单位用于计算，存储和显示总计时间，总分，总篮子总篮子总成果百分比，以及两个篮板组合中每一个的现场拍摄总分数。

3. 发明授权

US4904981A Multifunctional basketball game monitoring unit 失效
标题翻译：多功能篮球游戏监控单元
公开(公告)号：US4904981A
公开(公告)日：1990-02-27
申请号：US293703
申请日：1989-01-05
申请人： Thomas C. Mele , Mary K. Mele , Robert C. Dyer , Margaret A. Dyer
发明人： Thomas C. Mele , Mary K. Mele , Robert C. Dyer , Margaret A. Dyer
IPC分类号： A63B69/00 , A63B71/06 , G07C1/28
CPC分类号： G07C1/28 , A63B71/06 , A63B69/0071
摘要： A multifunctional basketball monitoring unit that allows visual display and print out of a total baskets made score and the percentage of total baskets made of total baskets attempted in free throw and goal shooting either under time pressure or with no time limitation.
摘要翻译：一个多功能篮球监控单元，允许在整个篮子中进行视觉显示和打印，得分和总篮子总篮数的百分比，总篮子尝试在时间压力或时间限制下进行罚球和射门。

4. 发明授权

US07473655B2 Method for silicon based dielectric chemical vapor deposition 有权
标题翻译：硅基电介质化学气相沉积方法
公开(公告)号：US07473655B2
公开(公告)日：2009-01-06
申请号：US11155646
申请日：2005-06-17
申请人： Yaxin Wang , Yuji Maeda , Thomas C. Mele , Sean M. Seutter , Sanjeev Tandon , R. Suryanarayanan Iyer
发明人： Yaxin Wang , Yuji Maeda , Thomas C. Mele , Sean M. Seutter , Sanjeev Tandon , R. Suryanarayanan Iyer
IPC分类号： H01L21/31
CPC分类号： H01L21/3185 , C23C16/345 , C23C16/45525 , C23C16/45553 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： Embodiments of the invention generally provide a method for depositing silicon-containing films. In one embodiment, a method for depositing silicon-containing material film on a substrate includes flowing a nitrogen and carbon containing chemical into a deposition chamber, flowing a silicon-containing source chemical having silicon-nitrogen bonds into the processing chamber, and heating the substrate disposed in the chamber to a temperature less than about 550 degrees Celsius. In another embodiment, the silicon containing chemical is trisilylamine and the nitrogen and carbon containing chemical is (CH3)3—N.
摘要翻译：本发明的实施方案通常提供一种沉积含硅膜的方法。在一个实施例中，将含硅材料膜沉积在基板上的方法包括将含氮和碳的化学品流入沉积室，将含有硅 - 氮键的含硅源化学品流入处理室，并加热基板置于室内至低于约550摄氏度的温度。在另一个实施方案中，含硅化学品是三甲基胺，含氮和碳的化学品是（CH 3）3 -N。

5. 发明授权

US5268590A CMOS device and process 失效
标题翻译： CMOS器件和工艺
公开(公告)号：US5268590A
公开(公告)日：1993-12-07
申请号：US958583
申请日：1992-10-08
申请人： James R. Pfiester , Thomas C. Mele , Young Limb
发明人： James R. Pfiester , Thomas C. Mele , Young Limb
IPC分类号： H01L21/336 , H01L21/768 , H01L21/8238 , H01L27/092 , H01L27/02
CPC分类号： H01L29/665 , H01L21/76885 , H01L21/8238 , H01L27/092 , Y10S257/915
摘要： A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.
摘要翻译：公开了一种CMOS器件及其制造方法。在一个实施例中，CMOS器件包括NMOS晶体管和PMOS晶体管，每个NMOS晶体管和PMOS晶体管都具有硅化源极和漏极区域，以及包括氮化钛阻挡层的硅栅电极。 NMOS晶体管和PMOS晶体管通过由氮化钛屏障材料层覆盖的硅层耦合在一起。源极和漏极区域被钴或其它金属硅化物硅化，其被防止与硅栅电极反应并且通过存在氮化钛阻挡层而互连。

6. 发明申请

US20090111284A1 METHOD FOR SILICON BASED DIELECTRIC CHEMICAL VAPOR DEPOSITION 审中-公开
标题翻译：基于硅的介电化学蒸气沉积方法
公开(公告)号：US20090111284A1
公开(公告)日：2009-04-30
申请号：US12348382
申请日：2009-01-05
申请人： Yaxin Wang , Yuji Maeda , Thomas C. Mele , Sean M. Seutter , Sanjeev Tandon , R. Suryanarayanan Iyer
发明人： Yaxin Wang , Yuji Maeda , Thomas C. Mele , Sean M. Seutter , Sanjeev Tandon , R. Suryanarayanan Iyer
IPC分类号： H01L21/314
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/45525 , C23C16/45553 , H01L21/02211 , H01L21/0228 , H01L21/3185 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： Embodiments of the invention generally provide a method for depositing silicon-containing films. In one embodiment, a method for depositing silicon-containing material film on a substrate includes heating a substrate disposed in a processing chamber to a temperature less than about 550 degrees Celsius; flowing a nitrogen and carbon containing chemical comprising (H3C)—N═N—H into the processing chamber; flowing a silicon-containing source chemical with silicon-nitrogen bonds into the processing chamber; and depositing a silicon and nitrogen containing film on the substrate.
摘要翻译：本发明的实施方案通常提供一种沉积含硅膜的方法。在一个实施例中，用于在衬底上沉积含硅材料膜的方法包括将设置在处理室中的衬底加热到低于约550摄氏度的温度; 将含有（H3C）-N-N-H的含氮和碳的化学品流入处理室; 将含有硅 - 氮键的含硅源化学品流入处理室; 以及在衬底上沉积含硅和氮的膜。

7. 发明授权

US5279978A Process for making BiCMOS device having an SOI substrate 失效
标题翻译：制造具有SOI衬底的BiCMOS器件的工艺
公开(公告)号：US5279978A
公开(公告)日：1994-01-18
申请号：US993282
申请日：1992-12-18
申请人： Yee-Chaung See , Thomas C. Mele , John R. Alvis
发明人： Yee-Chaung See , Thomas C. Mele , John R. Alvis
IPC分类号： H01L27/06 , H01L27/12 , H01L21/265
CPC分类号： H01L27/1203 , H01L27/0623 , Y10S148/009
摘要： A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer.In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region. An NMOS and a PMOS transistor are formed in the thin MOS region and are separated by a third isolation region extending from the first surface to the buried oxide layer. A vertical bipolar is formed in the electrically insulated bipolar region of the epitaxial layer.
摘要翻译：公开了一种BiCMOS器件和工艺，其中晶体管元件制造在SOI衬底上。使用SIMOX工艺在单晶硅衬底中形成掩埋氧化层，接着进行外延沉积，以形成覆盖掩埋氧化物层的不同厚度的硅体。然后在外延层的薄部分中形成MOS晶体管，并且在外延层的厚部分中形成垂直双极晶体管。根据本发明的一个实施例，提供单晶半导体衬底，其具有在第一表面下面的主表面和掩埋氧化物层。具有薄MOS区和厚双极区的第一导电类型的轻掺杂外延层覆盖在主表面上。从第一表面延伸到掩埋氧化物层的第一和第二隔离区域将双极区域与MOS区域分离并电绝缘。 NMOS和PMOS晶体管形成在薄MOS区中，并由从第一表面延伸到掩埋氧化物层的第三隔离区隔开。在外延层的电绝缘双极区域中形成垂直双极。

8. 发明授权

US5212397A BiCMOS device having an SOI substrate and process for making the same 失效
标题翻译：具有SOI衬底的BiCMOS器件及其制造方法
公开(公告)号：US5212397A
公开(公告)日：1993-05-18
申请号：US566901
申请日：1990-08-13
申请人： Yee-Chaung See , Thomas C. Mele , John R. Alvis
发明人： Yee-Chaung See , Thomas C. Mele , John R. Alvis
IPC分类号： H01L27/06 , H01L27/12
CPC分类号： H01L27/1203 , H01L27/0623 , Y10S148/009
摘要： A BiCMOS device and process are disclosed wherein the transistors components are fabricated on an SOI substrate. A SIMOX process is used to form a buried oxide layer in a single crystal silicon substrate followed by an epitaxial deposition to form a silicon body of varying thickness overlying the buried oxide layer. MOS transistors are then formed in a thin portion of the epitaxial layer and a vertical bipolar transistor is formed in the thick portion of the epitaxial layer. In accordance with one embodiment of the invention, a single crystal semiconductor substrate is provided having a principal surface and a buried oxide layer underlying the first surface. A lightly doped epitaxial layer of a first conductivity type having a thin MOS region and a thick bipolar region overlies the principal surface. A first and second isolation regions extending from the first surface to the buried oxide layer separate and electrically insulate the bipolar region from the MOS region. An NMOS and a PMOS transistor are formed in the thin MOS region and are separated by a third isolation region extending from the first surface to the buried oxide layer. A vertical bipolar is formed in the electrically insulated bipolar region of the epitaxial layer.
摘要翻译：公开了一种BiCMOS器件和工艺，其中晶体管元件制造在SOI衬底上。使用SIMOX工艺在单晶硅衬底中形成掩埋氧化层，接着进行外延沉积，以形成覆盖掩埋氧化物层的不同厚度的硅体。然后在外延层的薄部分中形成MOS晶体管，并且在外延层的厚部分中形成垂直双极晶体管。根据本发明的一个实施例，提供单晶半导体衬底，其具有在第一表面下面的主表面和掩埋氧化物层。具有薄MOS区和厚双极区的第一导电类型的轻掺杂外延层覆盖在主表面上。从第一表面延伸到掩埋氧化物层的第一和第二隔离区域将双极区域与MOS区域分离并电绝缘。 NMOS和PMOS晶体管形成在薄MOS区中，并由从第一表面延伸到掩埋氧化物层的第三隔离区隔开。在外延层的电绝缘双极区域中形成垂直双极。

9. 发明授权

US5101257A Semiconductor device having merged bipolar and MOS transistors and process for making the same 失效
标题翻译：具有合并双极和MOS晶体管的半导体器件及其制造方法
公开(公告)号：US5101257A
公开(公告)日：1992-03-31
申请号：US724285
申请日：1991-07-01
申请人： James D. Hayden , Thomas C. Mele , Frank K. Baker
发明人： James D. Hayden , Thomas C. Mele , Frank K. Baker
IPC分类号： H01L27/06 , H01L21/8249 , H01L27/07
CPC分类号： G11C13/003 , H01L27/0716 , G11C2213/74
摘要： A semiconductor device (10) has a bipolar transistor merged with an MOS transistor, the two transistors being separated essentially by a sidewall spacer and the bipolar transistor being self-aligned to the MOS transistor. The MOS transistor includes a gate (22) and a sorce region (38). A drain region of the MOS transistor is also an active base region (27) of the bipolar transistor. The bipoloar transistor further includes a first emitter region (40) formed in the active base region and a second emitter region (32) which is formed on the first emitter region and partially overlies the MOS transistor gate. The second emitter region is separated from the gate by a sidewall spacer (29) and an overlying dielectric layer (23).

10. 发明授权

US4997790A Process for forming a self-aligned contact structure 失效
标题翻译：用于形成自对准接触结构的方法
公开(公告)号：US4997790A
公开(公告)日：1991-03-05
申请号：US566185
申请日：1990-08-13
申请人： Michael P. Woo , Thomas C. Mele , Wayne J. Ray , Wayne M. Paulson
发明人： Michael P. Woo , Thomas C. Mele , Wayne J. Ray , Wayne M. Paulson
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/60 , H01L21/768
CPC分类号： H01L21/76897 , H01L21/76885 , H01L24/11 , Y10S148/105 , Y10S148/161
摘要： A self-aligned contact is formed in a multi-layer semiconductor device. In one form, conductive members are formed overlying a substrate material and a first insulating layer is deposited overlying the substrate material and the conductive members. A film of material is deposited on the first insulating layer and the film of material is patterned to form a sacrificial plug in an area where a contact is to be made. A second insulating layer is deposited on the device, and the device is made substantially planar. The second insulating layer is etched back to expose the sacrificial plug. The sacrificial plug is removed by selectively etching the device such that the first and second insulating layers are left substantially unaltered. An anisotropic etch of the device is performed to expose an area of the substrate material on which a contact is to be made, and to simultaneously form sidewall spacers along edges of the conductive members. A conductive layer is deposited onto the device and patterned, thereby forming a self-aligned contact.
摘要翻译：在多层半导体器件中形成自对准接触。在一种形式中，形成覆盖衬底材料的导电构件，并且沉积覆盖衬底材料和导电构件的第一绝缘层。将材料膜沉积在第一绝缘层上，并且将材料膜图案化以在要进行接触的区域中形成牺牲插塞。第二绝缘层沉积在器件上，并且器件基本上是平面的。将第二绝缘层回蚀刻以暴露牺牲插头。通过选择性地蚀刻该器件以使得第一绝缘层和第二绝缘层基本上保持不变而去除牺牲插塞。执行器件的各向异性蚀刻以暴露要在其上形成触点的衬底材料的区域，并且同时沿着导电构件的边缘形成侧壁间隔物。导电层沉积在器件上并图案化，从而形成自对准接触。

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