专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07840867B2 Iterative n-dimensional decoding 有权
标题翻译：迭代n维解码
公开(公告)号：US07840867B2
公开(公告)日：2010-11-23
申请号：US10992650
申请日：2004-11-22
申请人： Silvio Cucchi , Sonia Rinaldi , Gianluca Macheda
发明人： Silvio Cucchi , Sonia Rinaldi , Gianluca Macheda
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： H03M13/2948 , H03M13/151 , H03M13/29 , H03M13/293
摘要： A method for performing an iterative n-dimensional decoding of a data structure comprising a data bit frame. The method includes receiving possibly errored data; computing syndromes in all the n dimensions in a single step; storing the first calculated syndromes; processing syndromes in a first dimension; correcting errors; and updating the syndromes which have been affected by the correction in the first dimension; and processing syndromes in all the possible dimensions up to the n-th one and, for each of the processed syndromes, correcting errors and updating the syndromes in all the dimensions which have been affected by the correction. The time required by each sub-iteration (from second sub-iteration on) will be progressively reduced. The number of iterations is increased without increasing the delay and processing complexity.
摘要翻译：一种用于对包括数据位帧的数据结构进行迭代n维解码的方法。该方法包括接收可能的错误数据; 在单个步骤中计算所有n维的综合征; 存储第一个计算的综合征; 第一维处理综合征; 纠正错误; 并更新在第一维度中受到校正影响的综合征; 以及在所有可能尺寸直到第n个处理综合征，并且对于每个经处理的综合征，校正错误并更新已经受校正影响的所有维度的综合征。每个子迭代（从第二次迭代开始）所需的时间将逐渐减少。迭代次数增加而不增加延迟和处理复杂度。

2. 发明申请

US20070133613A1 METHOD AND DEVICE FOR DEMAPPING A TRIBUTARY RECOVERING LOWER ORDER SYNCHRONISM 有权
标题翻译：用于描述记录恢复下位同步的方法和装置
公开(公告)号：US20070133613A1
公开(公告)日：2007-06-14
申请号：US11610515
申请日：2006-12-14
申请人： Luca Razzetti , Sonia Rinaldi , Paolo Sorge
发明人： Luca Razzetti , Sonia Rinaldi , Paolo Sorge
IPC分类号： H04J3/06
CPC分类号： H04J3/07 , H04J3/1611
摘要： It is disclosed a method of demapping a tributary from a first frame into a second frame, the first frame comprising a plurality of tributary words and a synchronization word, the method comprising: providing a first and a second counters; increasing the first counter by a first value at each clock cycle of the second frame; and performing reading operations according to the second counter. It further comprises: generating synchronization information according to the synchronization word; according to the synchronization information, performing a change of state between a first state and a second state, wherein, in the first state, the second counter is synchronized to the first counter at each clock cycle of the second frame, and in the second state, the second counter is synchronized to the first counter at a predetermined instant of the second frame and the second counter is increased by a second value at each clock cycle of the second frame wherein the reading operation is performed.
摘要翻译：公开了一种将支路从第一帧解映射到第二帧中的方法，所述第一帧包括多个辅助字和同步字，所述方法包括：提供第一和第二计数器; 在第二帧的每个时钟周期将第一计数器增加第一值; 并根据第二计数器执行读取操作。它还包括：根据同步字产生同步信息; 根据同步信息，执行第一状态和第二状态之间的状态改变，其中，在第一状态下，第二计数器在第二帧的每个时钟周期与第一计数器同步，并且在第二状态，第二计数器在第二帧的预定时刻与第一计数器同步，并且在执行读取操作的第二帧的每个时钟周期将第二计数器增加第二值。

3. 发明申请

US20070009063A1 Method and device for mapping/demapping a tributary signal into/from a synchronous frame 审中-公开
标题翻译：用于将支路信号映射/解映射到/从同步帧中的方法和设备
公开(公告)号：US20070009063A1
公开(公告)日：2007-01-11
申请号：US11447791
申请日：2006-06-07
申请人： Sonia Rinaldi , Luca Razzetti , Stefano Gastaldello
发明人： Sonia Rinaldi , Luca Razzetti , Stefano Gastaldello
IPC分类号： H04L27/36 , H03D1/24
CPC分类号： H04J3/076
摘要： It is disclosed a mapper for mapping a tributary from a first frame into a second frame. The mapper comprises: a first register for generating a first counter which is adapted to be increased by a first value at each clock cycle of the first frame; a second register for generating a second counter which is adapted to be increased by a second value at each clock cycle of the second frame; a difference module for calculating a phase error between the first counter and the second counter; and a frame generation module, responsive to the phase error, for mapping the tributary into the second frame.
摘要翻译：公开了一种用于将支路从第一帧映射到第二帧的映射器。映射器包括：第一寄存器，用于产生适于在第一帧的每个时钟周期增加第一值的第一计数器; 第二寄存器，用于产生适于在第二帧的每个时钟周期增加第二值的第二计数器; 用于计算第一计数器和第二计数器之间的相位误差的差分模块; 以及响应于相位误差的帧生成模块，用于将支路映射到第二帧中。

4. 发明申请

US20050204254A1 Erasure FEC decoder and method 有权
标题翻译：擦除FEC解码器和方法
公开(公告)号：US20050204254A1
公开(公告)日：2005-09-15
申请号：US11012302
申请日：2004-12-16
申请人： Silvio Cucchi , Sonia Rinaldi , Marco Andreasi
发明人： Silvio Cucchi , Sonia Rinaldi , Marco Andreasi
IPC分类号： H03M13/29 , H03M13/00
CPC分类号： H03M13/2948 , H03M13/152 , H03M13/2909 , H03M13/293
摘要： Disclosed is a method and erasure FEC decoder for correcting a pattern of errors by a two-dimensional decoding, the pattern of errors comprising at least two codewords in both a first and a second dimensions with a number of errors in common higher than the capacity of the code which is used for decoding. The method comprises the steps of: performing a full capacity decoding along the second dimension for removing possible false corrections introduced by a previous decoding performed along the first dimension; performing a reduced-capacity decoding along the first dimension, for identifying errored codewords along the first dimension; performing a full capacity decoding along the second dimension with disabled correction feature for identifying errored codewords along the second dimension; detecting the error coordinates from the information from steps b) and c); and correcting the detected pattern of errors.
摘要翻译：公开了一种用于通过二维解码来校正错误模式的方法和擦除FEC解码器，错误模式包括在第一和第二维度中的至少两个码字，其中多个错误共同高于用于解码的代码。该方法包括以下步骤：沿着第二维执行全容量解码，以去除沿着第一维度执行的先前解码引入的可能的伪校正; 沿着第一维度执行简化容量解码，用于识别沿着第一维度的错误码字; 沿着所述第二维度执行具有禁用校正特征的全容量解码，用于识别沿着所述第二维度的错误码字; 根据来自步骤b）和c）的信息检测误差坐标; 并校正检测到的错误模式。

5. 发明授权

US08165174B2 Method and device for demapping a tributary recovering lower order synchronism 有权
标题翻译：解决支流恢复低阶同步的方法和装置
公开(公告)号：US08165174B2
公开(公告)日：2012-04-24
申请号：US11610515
申请日：2006-12-14
申请人： Luca Gabriele Razzetti , Sonia Rinaldi , Paolo Sorge
发明人： Luca Gabriele Razzetti , Sonia Rinaldi , Paolo Sorge
IPC分类号： H04J3/06
CPC分类号： H04J3/07 , H04J3/1611
摘要： In a method of demapping a tributary from a first frame into a second frame, the first frame has a plurality of tributary words and a synchronization word, and first and second counters are provided. The first counter is increased by a first value at each dock cycle of the second frame, and reading operations are performed according to the second counter. Synchronization information, generated according to the synchronization word, is used to change between first and second states. When in the first state, the second counter is synchronized to the first counter at each clock cycle of the second frame; and, when in the second state, the second counter is synchronized to the first counter at a predetermined instant of the second frame, the second counter increasing by a second value at each clock cycle of the second frame wherein the reading operation is performed.
摘要翻译：在将支路从第一帧解映射到第二帧的方法中，第一帧具有多个辅助字和同步字，并且提供第一和第二计数器。第一计数器在第二帧的每个停靠周期处增加第一值，并且根据第二计数器执行读取操作。根据同步字生成的同步信息用于在第一和第二状态之间切换。当处于第一状态时，第二计数器在第二帧的每个时钟周期与第一计数器同步; 并且当处于第二状态时，第二计数器在第二帧的预定时刻与第一计数器同步，第二计数器在执行读取操作的第二帧的每个时钟周期处增加第二值。

6. 发明授权

US07346826B2 Erasure FEC decoder and method 有权
标题翻译：擦除FEC解码器和方法
公开(公告)号：US07346826B2
公开(公告)日：2008-03-18
申请号：US11012302
申请日：2004-12-16
申请人： Silvio Cucchi , Sonia Rinaldi , Marco Andreasi
发明人： Silvio Cucchi , Sonia Rinaldi , Marco Andreasi
IPC分类号： H03M13/00
CPC分类号： H03M13/2948 , H03M13/152 , H03M13/2909 , H03M13/293
摘要： Disclosed is a method and erasure FEC decoder for correcting a pattern of errors by a two-dimensional decoding, the pattern of errors comprising at least two codewords in both a first and a second dimensions with a number of errors in common higher than the capacity of the code which is used for decoding. The method comprises the steps of: performing a full capacity decoding along the second dimension for removing possible false corrections introduced by a previous decoding performed along the first dimension; performing a reduced-capacity decoding along the first dimension, for identifying errored codewords along the first dimension; performing a full capacity decoding along the second dimension with disabled correction feature for identifying errored codewords along the second dimension; detecting the error coordinates from the information from steps b) and c); and correcting the detected pattern of errors.
摘要翻译：公开了一种用于通过二维解码来校正错误模式的方法和擦除FEC解码器，错误模式包括第一和第二维度中的至少两个码字，其中多个错误共同高于用于解码的代码。该方法包括以下步骤：沿着第二维执行全容量解码，以去除沿着第一维度执行的先前解码引入的可能的伪校正; 沿着第一维度执行简化容量解码，用于识别沿着第一维度的错误码字; 沿着所述第二维度执行具有禁用校正特征的全容量解码，用于识别沿着所述第二维度的错误码字; 根据来自步骤b）和c）的信息检测误差坐标; 并校正检测到的错误模式。

7. 发明申请

US20050182998A1 Iterative n-dimensional decoding 有权
标题翻译：迭代n维解码
公开(公告)号：US20050182998A1
公开(公告)日：2005-08-18
申请号：US10992650
申请日：2004-11-22
申请人： Silvio Cucchi , Sonia Rinaldi , Gianluca Macheda
发明人： Silvio Cucchi , Sonia Rinaldi , Gianluca Macheda
IPC分类号： H03M13/15 , H03M13/29 , H03M13/00
CPC分类号： H03M13/2948 , H03M13/151 , H03M13/29 , H03M13/293
摘要： Disclosed is a method for performing an iterative n-dimensional decoding of a data structure comprising a data bit frame. The method comprises the steps of: receiving possibly errored data; computing syndromes in all the n dimensions in a single step; storing the first calculated syndromes; processing syndromes in a first dimension; correcting errors; and updating the syndromes which have been affected by the correction in said first dimension; and processing syndromes in all the possible dimensions up to the n-th one and, for each of the processed syndromes, correcting errors and updating the syndromes in all the dimensions which have been affected by the correction. The time required by each sub-iteration (from second sub-iteration on) will be progressively reduced. The number of iterations is increased without increasing the delay and processing complexity. Processing complexity is reduced because only one circuit is used for processing the syndromes in all the dimensions and for all the iterations.
摘要翻译：公开了一种用于对包括数据位帧的数据结构执行迭代n维解码的方法。该方法包括以下步骤：接收可能的错误数据; 在单个步骤中计算所有n维的综合征; 存储第一个计算的综合征; 第一维处理综合征; 纠正错误; 以及更新已经受到所述第一维度中的校正的影响的综合征; 以及在所有可能尺寸直到第n个处理综合征，并且对于每个经处理的综合征，校正错误并更新已经受校正影响的所有维度的综合征。每个子迭代（从第二次迭代开始）所需的时间将逐渐减少。迭代次数增加而不增加延迟和处理复杂度。减少处理复杂度，因为在所有维度和所有迭代中仅使用一个电路来处理综合征。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式