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1. 发明申请

US20110079858A1 SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET 有权
标题翻译：具有放大偏差的感测放大器电路的半导体存储器件
公开(公告)号：US20110079858A1
公开(公告)日：2011-04-07
申请号：US12967728
申请日：2010-12-14
申请人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru Akiyama , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： H01L27/108
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译：具有高集成度，低功耗和高操作速度的半导体存储器件。存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。

2. 发明申请

US20100164607A1 SEMICONDUCTOR DEVICE THAT CAN ADJUST SUBSTRATE VOLTAGE 有权
标题翻译：可调节基极电压的半导体器件
公开(公告)号：US20100164607A1
公开(公告)日：2010-07-01
申请号：US12647259
申请日：2009-12-24
申请人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
发明人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
IPC分类号： G05F1/10
CPC分类号： G05F3/205 , G05F1/46
摘要： To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.
摘要翻译：为了提供一种半导体器件，包括：形成在半导体衬底中并具有要调节的阈值电压的MOS晶体管，MOS晶体管的复制晶体管，监视电路监视当复制晶体管流过具有给定的设计值，负电压泵浦电路基于监控电路的输出产生MOS晶体管的衬底电压，并且限制电路定义负电压抽运电路的操作，而不管监视的监视结果如何电路，响应于相对于预定值的衬底电压的过量。

3. 发明授权

US07554863B2 Voltage control circuit and semiconductor device having the voltage control circuit 有权
标题翻译：电压控制电路和具有电压控制电路的半导体器件
公开(公告)号：US07554863B2
公开(公告)日：2009-06-30
申请号：US11580191
申请日：2006-10-13
申请人： Motohiro Tabuchi , Shinichi Miyatake
发明人： Motohiro Tabuchi , Shinichi Miyatake
IPC分类号： G11C7/00
CPC分类号： G11C5/145
摘要： A voltage control circuit of the present invention is applicable to a combination of a decoder circuit and a level conversion circuit connected to the decoder circuit. The voltage control circuit includes a level conversion circuit voltage line for applying a voltage to the level conversion circuit, and a boost voltage connection switch for switching a voltage applied to the level conversion circuit voltage line according to an output signal from the decoder circuit. This configuration makes it possible to prevent, when a boost voltage is applied to the level conversion circuit, the breakdown of transistors in the level conversion circuit due to a ripple in the boost voltage.
摘要翻译：本发明的电压控制电路可应用于解码器电路和连接到解码器电路的电平转换电路的组合。电压控制电路包括用于向电平转换电路施加电压的电平转换电路电压线和用于根据来自解码器电路的输出信号切换施加到电平转换电路电压线的电压的升压电压连接开关。这种配置使得可以在对电平转换电路施加升压电压时，防止由于升压电压中的纹波引起的电平转换电路中的晶体管的击穿。

4. 发明申请

US20080175084A1 SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER CIRCUIT 有权
标题翻译：半导体存储器件和感测放大器电路
公开(公告)号：US20080175084A1
公开(公告)日：2008-07-24
申请号：US11969223
申请日：2008-01-03
申请人： Satoru AKIYAMA , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru AKIYAMA , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译：一种具有高集成度，低功耗和高运行速度的半导体存储器件，包括具有多个下拉电路和上拉电路的读出放大器电路，其中构成多个下拉电路中的一个的晶体管具有比构成其他下拉电路的晶体管（例如沟道长度和沟道宽度）的常数大的常数，在多个下拉电路中具有较大的晶体管常数的下拉电路先前被激活，然后另一个下拉电路和上拉电路被激活以进行读取，此外，数据线和先前驱动的下拉电路通过NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制激活或下拉电路失活。

5. 发明申请

US20070096958A1 Voltage control circuit and semiconductor device having the voltage control circuit 有权
标题翻译：电压控制电路和具有电压控制电路的半导体器件
公开(公告)号：US20070096958A1
公开(公告)日：2007-05-03
申请号：US11580191
申请日：2006-10-13
申请人： Motohiro Tabuchi , Shinichi Miyatake
发明人： Motohiro Tabuchi , Shinichi Miyatake
IPC分类号： H03M7/38
CPC分类号： G11C5/145
摘要： A voltage control circuit of the present invention is applicable to a combination of a decoder circuit and a level conversion circuit connected to the decoder circuit. The voltage control circuit includes a level conversion circuit voltage line for applying a voltage to the level conversion circuit, and a boost voltage connection switch for switching a voltage applied to the level conversion circuit voltage line according to an output signal from the decoder circuit. This configuration makes it possible to prevent, when a boost voltage is applied to the level conversion circuit, the breakdown of transistors in the level conversion circuit due to a ripple in the boost voltage.
摘要翻译：本发明的电压控制电路可应用于解码器电路和连接到解码器电路的电平转换电路的组合。电压控制电路包括用于向电平转换电路施加电压的电平转换电路电压线和用于根据来自解码器电路的输出信号切换施加到电平转换电路电压线的电压的升压电压连接开关。这种配置使得可以在对电平转换电路施加升压电压时，防止由于升压电压中的纹波引起的电平转换电路中的晶体管的击穿。

6. 发明申请

US20050056876A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050056876A1
公开(公告)日：2005-03-17
申请号：US10975494
申请日：2004-10-29
申请人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
发明人： Shinichi Miyatake , Kazuhiko Kajigaya , Kazuyuki Miyazawa , Tomonori Sekiguchi , Riichiro Takemura , Takeshi Sakata
IPC分类号： G11C11/401 , G11C7/18 , G11C11/403 , G11C11/405 , G11C11/406 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/0328 , H01L31/119
CPC分类号： H01L27/108 , G11C7/18 , G11C11/403 , G11C11/406 , G11C11/40615 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10814 , H01L27/10885 , H01L27/10897 , Y10S257/905 , Y10S257/906
摘要： A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
摘要翻译：提供一种半导体存储器件，其可以通过减少存储器单元的面积的增加并获得超宽带的周期，实现信息保持时间期间的高集成度，超高速度运行和功耗的显着降低，高速读出时间，确保自刷新时间长的刷新周期。采用单交点单元两个单元/位方法的DRAM具有采用单交叉6 F 2单元的双单元结构，其结构是：存储单元布置在对应于a 位线对和字线; 并且当字线的半间距被定义为F时，位线对的每个位线的间距大于2F且小于4F。另外，硅衬底中的有源区域形成每个存储单元的晶体管的源极，沟道和漏极，相对于位线对的方向倾斜地形成。

7. 发明授权

US06633508B2 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US06633508B2
公开(公告)日：2003-10-14
申请号：US09939677
申请日：2001-08-28
申请人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
发明人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
IPC分类号： G11C700
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1051 , G11C11/406 , G11C11/40626 , G11C11/4096
摘要： Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.
摘要翻译：根据特定写入操作模式的指定，同时选择不同存储器阵列中的两个存储器单元，以将写入信号的逻辑1与每个电容器中存在电荷的状态相关联。此外，写入信号的逻辑0与在电容器中不存在电荷以写入相同写入信号的状态相关联。根据特定读取操作模式的指定，同时选择不同存储器阵列中的两个动态存储单元，以将每个动态存储单元的电容器中存在电荷的状态与读取信号的逻辑1和关联响应于写入操作，具有读取信号的逻辑0的电容器中不存在电荷的状态。因此，优先输出两个读取信号的逻辑1。

8. 发明授权

US5983358A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5983358A
公开(公告)日：1999-11-09
申请号：US938962
申请日：1997-09-26
申请人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
IPC分类号： G11C11/401 , G06F11/00 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.
摘要翻译：具有冗余电路的半导体存储器包括判断装置，用于接收用于存储缺陷地址的第一ROM的输出，并判断有缺陷的存储单元和备用存储单元是否属于同一个存储单元，并且还包括定时调整电路，用于根据判断装置的输出来改变施加到存储器垫控制电路的控制信号的定时。当有缺陷的和备用的存储器单元属于相同的存储器存储器时，控制信号的定时变得快。

9. 发明授权

US5905685A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US5905685A
公开(公告)日：1999-05-18
申请号：US951734
申请日：1997-10-15
申请人： Masayuki Nakamura , Masatoshi Hasegawa , Seiji Narui , Yousuke Tanaka , Shinichi Miyatake , Shuichi Kubouchi , Kazuhiko Kajigaya
发明人： Masayuki Nakamura , Masatoshi Hasegawa , Seiji Narui , Yousuke Tanaka , Shinichi Miyatake , Shuichi Kubouchi , Kazuhiko Kajigaya
IPC分类号： G11C11/407 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4074 , G11C11/408 , G11C11/4087
摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.
摘要翻译：在具有存储单元阵列的动态RAM中，其中动态存储单元布置在字线和一对位线中的一个位线之间的交叉点处，对应于电源电压的选择电平信号和对应于低于电路接地电位的负电位被提供给字线。通过由电路接地电位进行工作的读出放大器对一对位线读取的存储单元的信号和通过将电源电压降低等于地址选择MOSFET的阈值电压的量而形成的内部电压被放大。动态RAM具有接收电源电压和电路接地电位的振荡器，以及接收由振荡器产生的振荡脉冲以产生负电位的电路。

10. 发明授权

US5818784A Semiconductor memory device and memory system 失效
公开(公告)号：US5818784A
公开(公告)日：1998-10-06
申请号：US638128
申请日：1996-04-26
申请人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
发明人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
IPC分类号： G11C11/403 , G11C7/04 , G11C7/10 , G11C11/406 , G11C11/4096 , H01L27/10
CPC分类号： G11C7/1069 , G11C11/406 , G11C11/40626 , G11C11/4096 , G11C7/1006 , G11C7/1051
摘要： Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

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