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1. 发明授权

US10836765B2 Process for the preparation of valacyclovir 有权
公开(公告)号：US10836765B2
公开(公告)日：2020-11-17
申请号：US16081944
申请日：2017-02-24
申请人： AUROBINDO PHARMA LTD , Sandeep Jain , Komel Ansari , Subramanyam Maddala , Sivakumaran Meenakshisundaram
发明人： Sandeep Jain , Komel Ansari , Subramanyam Maddala , Sivakumaran Meenakshisundaram
IPC分类号： C07D473/18 , B01J19/00
CPC分类号： C07D473/18 , B01J19/0093 , B01J2219/00033
摘要： The present invention relates to an improved process for the preparation of Valacyclovir or pharmaceutically acceptable salts thereof, which comprises reaction of amine-protected Valacyclovir or its salt with deprotecting agent in a continuous flow reactor.

2. 发明授权

US10505871B1 Future messaging maximizing contextual relevancy and minimizing information overload based distractions 有权
公开(公告)号：US10505871B1
公开(公告)日：2019-12-10
申请号：US15827172
申请日：2017-11-30
申请人： Sandeep Jain
发明人： Sandeep Jain
IPC分类号： H04L12/58
CPC分类号： H04L51/04 , H04L51/12 , H04L51/24 , H04L51/28
摘要： A messaging server with a future message storage space for future messages, each being a sender created message not yet delivered to a recipient that has an associated sender specified message delivery time. Recipient specific delivery block details are specified for a set of delivery blocks for future messages. The future messages are received processed and stored. Until the respective sender specified message delivery time a respective one of the set of senders is able to retract and edit a corresponding one of the future messages. Future messages are delivered at the delivery time consistent with the delivery blocks. After delivery the sender is unable to retract and edit a corresponding delivered message. Future messages do not alert a recipient of arrival until the sender established delivery time, which minimizes cognitive distractions and provides the sender with notice for anticipating a time of response, without overly distracting the recipient.

3. 发明授权

US09229890B2 Method and a system for integrating data from a source to a destination 有权
标题翻译：方法和用于将数据从源到目标集成的系统
公开(公告)号：US09229890B2
公开(公告)日：2016-01-05
申请号：US13457497
申请日：2012-04-27
申请人： Sandeep Jain , Prakash Chandra Tiwary
发明人： Sandeep Jain , Prakash Chandra Tiwary
IPC分类号： G06F17/30 , G06F13/22
CPC分类号： G06F13/22 , G06F11/2082 , G06F17/30008 , G06F17/30575
摘要： The embodiments herein provide a system and a method for integrating a data from a source to a destination. The method comprises generating a global-id, setting an event-id corresponding to an entity id in the global id, polling a data from a source, sorting changes of a source system based on a time of update and an entity id, creating and comparing an old as of state value and a new as of state value for each field for each update in the entity in the source and destination to detect a conflict on an entity, sending a time of update in the entity and a revision id of a change to the destination, comparing the global id with an event id for each entity at the destination to detect a presence of an entity in the destination and processing an entity at the destination based an event id.
摘要翻译：这里的实施例提供了用于将来自源到目的地的数据进行集成的系统和方法。该方法包括生成global-id，设置与全局id中的实体id相对应的事件id，轮询来自源的数据，根据更新时间和实体id对源系统的改变进行排序，创建和将来自源和目的地中的实体中的每个更新的每个字段的状态值和状态值的新的状态值进行比较以检测实体上的冲突，在实体中发送更新时间和修改ID 将目的地的每个实体的全局id与事件ID进行比较，以检测目的地中的实体的存在并根据事件ID处理目的地的实体。

4. 发明授权

US09053035B1 Multi-threaded system for performing atomic binary translations 有权
标题翻译：用于执行原子二进制翻译的多线程系统
公开(公告)号：US09053035B1
公开(公告)日：2015-06-09
申请号：US14088446
申请日：2013-11-25
申请人： Ashish Mathur , Sandeep Jain
发明人： Ashish Mathur , Sandeep Jain
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F9/3004 , G06F8/45 , G06F8/52 , G06F9/45558
摘要： A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.
摘要翻译：多线程二进制翻译系统通过线程执行原子操作，这样的操作包括处理加载链接指令和存储条件指令。存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。条件是：负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同，保留标志指示线程具有有效预留，以及负载存储的数据副本链接指令与存储在存储条件共享存储器地址中的数据相同。

5. 发明申请

US20150149725A1 MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS 有权
标题翻译：用于执行原子二进制翻译的多线程系统
公开(公告)号：US20150149725A1
公开(公告)日：2015-05-28
申请号：US14088446
申请日：2013-11-25
申请人： Ashish Mathur , Sandeep Jain
发明人： Ashish Mathur , Sandeep Jain
IPC分类号： G06F12/08
CPC分类号： G06F9/3004 , G06F8/45 , G06F8/52 , G06F9/45558
摘要： A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.
摘要翻译：多线程二进制翻译系统通过线程执行原子操作，这样的操作包括处理加载链接指令和存储条件指令。存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。条件是：负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同，保留标志指示线程具有有效预留，以及负载存储的数据副本链接指令与存储在存储条件共享存储器地址中的数据相同。

6. 发明申请

US20150121127A1 WATCHPOINT SUPPORT SYSTEM FOR FUNCTIONAL SIMULATOR 有权
标题翻译：功能模拟器的观察支持系统
公开(公告)号：US20150121127A1
公开(公告)日：2015-04-30
申请号：US14067920
申请日：2013-10-30
申请人： Sandeep Jain
发明人： Sandeep Jain
IPC分类号： G06F11/14
CPC分类号： G06F11/1402 , G06F11/3636 , G06F12/0802 , G06F12/0875
摘要： A functional simulator with watchpoint support includes a CPU having a first-level DMI cache, a watchpoint manager having a second-level DMI cache, an interconnect module, and a memory controller. The simulator is operated by a front-end tool. Watchpoints corresponding to a predetermined memory addresses are set by the front-end tool and stored as a watchpoint address list in the watchpoint manager. When a memory access request is received by the first-level DMI cache, after a failure to complete the memory access request, the CPU transmits the request to the watchpoint manager. The watchpoint manager searches for a memory address associated with the memory access request in the watchpoint address list. If a match is found, the watchpoint manager generates a watchpoint hit signal and notifies the front-end tool.
摘要翻译：具有观察点支持的功能模拟器包括具有第一级DMI缓存的CPU，具有二级DMI高速缓存的观察点管理器，互连模块和存储器控制器。模拟器由前端工具操作。与预定存储器地址相对应的观察点由前端工具设置，并作为观察点地址列表存储在观察点管理器中。当第一级DMI缓存接收到存储器访问请求时，在完成存储器访问请求失败之后，CPU将该请求发送给观察点管理器。观察点管理器在观察点地址列表中搜索与存储器访问请求相关联的存储器地址。如果找到匹配，则观察点管理器生成观察点命中信号并通知前端工具。

7. 发明授权

US07809827B1 Network device having service card for lawful intercept and monitoring of packet flows 有权
标题翻译：网络设备具有合法拦截和监控分组流的业务卡
公开(公告)号：US07809827B1
公开(公告)日：2010-10-05
申请号：US11516878
申请日：2006-09-07
申请人： Manoj Apte , Sandeep Jain , Fritz Budiyanto , Senthil Kumar Duraiswamy , Saravanan Deenadayalan , Yulianto Kokasih Ko
发明人： Manoj Apte , Sandeep Jain , Fritz Budiyanto , Senthil Kumar Duraiswamy , Saravanan Deenadayalan , Yulianto Kokasih Ko
IPC分类号： G06F15/173
CPC分类号： H04L43/028 , H04L45/10 , H04L45/38
摘要： A network device comprises a service card (e.g., a lawful intercept (LI) service card) executing a communication protocol to receive, from one or more sources (e.g., law enforcement agents), intercept information specifying at least one destination and criteria for matching one or more packet flows. The network device further includes a network interface card to receive a packet from a network, and a control unit to provide the packet from the interface card to the LI service card. The LI service card executes a flow match detection module that, when the packet matches the criteria of the intercept information, forwards the packet to the destination specified by the intercept information. The network device may provide real-time intercept and relaying of specified network-based communications. Moreover, the techniques described herein allow LEAs to tap packet flows with little delay after specifying intercept information, e.g., within 50 milliseconds, even under high-volume networks.
摘要翻译：网络设备包括执行通信协议的服务卡（例如合法拦截（LI）服务卡），以从一个或多个来源（例如执法人员）接收指定至少一个目的地的拦截信息和用于匹配的标准一个或多个分组流。网络设备还包括从网络接收分组的网络接口卡，以及将接口卡向L1服务卡提供分组的控制单元。 LI服务卡执行流匹配检测模块，当分组符合拦截信息的标准时，将分组转发到由拦截信息指定的目的地。网络设备可以提供指定的基于网络的通信的实时拦截和中继。此外，即使在高容量网络下，本文所描述的技术允许LEA在指定拦截信息（例如，在50毫秒内）之后稍微延迟地敲击分组流。

8. 发明授权

US07793037B2 Partial page scheme for memory technologies 有权
标题翻译：内存技术部分页面方案
公开(公告)号：US07793037B2
公开(公告)日：2010-09-07
申请号：US11140772
申请日：2005-05-31
申请人： Sandeep Jain , Animesh Mishra , Jim Kardach
发明人： Sandeep Jain , Animesh Mishra , Jim Kardach
IPC分类号： G06F12/00
CPC分类号： G11C7/1021 , G11C7/1045 , G11C8/12
摘要： Systems and methods of managing memory provide for detecting a request to activate a memory portion that is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request may include identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.
摘要翻译：管理存储器的系统和方法提供用于检测激活被限制为部分页面大小的部分页面大小的存储器部分的请求，其中部分页面大小小于与存储器相关联的整个页面大小。在一个实施例中，检测请求可以包括识别与该请求相关联的行地址和部分页面地址，其中部分页面地址指示存储器部分被限制为部分页面大小。

9. 发明申请

US20100168849A1 TRANSCORNEAL VISION ASSISTANCE DEVICE 有权
标题翻译：交叉视力辅助装置
公开(公告)号：US20100168849A1
公开(公告)日：2010-07-01
申请号：US12600967
申请日：2008-03-13
申请人： Dimitri Azar , Jose De La Cruz , Sandeep Jain
发明人： Dimitri Azar , Jose De La Cruz , Sandeep Jain
IPC分类号： A61F2/14
CPC分类号： A61F2/1651 , A61F2/14 , A61F2/142 , A61F2/15 , A61F2220/0008
摘要： The invention provides a transcorneal vision assistance device implantable in the eye of a patient. A preferred embodiment transcorneal microtelescope vision assistance device is implantable in the eye of a patient and includes a keratoprosthesis configured to replace a portion of the cornea of a patient and to secure the keratoprosthesis to a remaining front portion of the cornea. A microtelescope is carried by the keratoprosthesis for transcorneal mounting of the microtelescope.
摘要翻译：本发明提供了一种可植入患者眼中的视神经视像辅助装置。优选的实施方式，转角镜微视野镜视觉辅助装置可植入患者的眼睛中，并且包括构造成替换患者角膜的一部分并将角膜假体固定到角膜的剩余前部的角膜假体。微型望远镜由角膜假体承载，用于微型望远镜的经角膜安装。

10. 发明授权

US07454639B2 Various apparatuses and methods for reduced power states in system memory 有权
标题翻译：用于在系统存储器中降低功率状态的各种装置和方法
公开(公告)号：US07454639B2
公开(公告)日：2008-11-18
申请号：US11174060
申请日：2005-06-30
申请人： Sandeep Jain , James P. Kardach
发明人： Sandeep Jain , James P. Kardach
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/14
摘要： A method, apparatus, and system are described in which a memory controller may have two or more registers to create and track zones of memory in a volatile memory device. The memory controller controls a power consumption state of a first zone of memory in the volatile memory device and a second zone of memory within the first volatile memory device on an individual basis; and one or more memory arrays contained within the first volatile memory device.
摘要翻译：描述了一种方法，装置和系统，其中存储器控制器可以具有两个或更多个寄存器来创建和跟踪易失性存储器设备中的存储器区域。存储器控制器在单独的基础上控制易失性存储器设备中的第一存储器区域和第一易失性存储器设备内的第二存储器区域的功耗状态; 以及包含在第一易失性存储器件内的一个或多个存储器阵列。

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