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1. 发明申请

US20160056159A1 SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS OVERLAPPING ASSOCIATED BITLINE STRUCTURES AND CONTACT HOLES AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有接触片的半导体器件重叠相关的位线结构和接触孔及其制造方法
公开(公告)号：US20160056159A1
公开(公告)日：2016-02-25
申请号：US14754040
申请日：2015-06-29
申请人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
发明人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
IPC分类号： H01L27/108 , H01L23/535
CPC分类号： H01L27/10885 , H01L21/76879 , H01L27/10814 , H01L27/10817 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.
摘要翻译：半导体器件可以包括根据衬底上的布局布置的多个着陆焊盘，其中每个着陆焊盘的横截面形状具有菱形形状，使得菱形形状的相对内部角度彼此相等，并且钻石形状的相邻内角彼此不相等。

2. 发明申请

US20120273741A1 PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20120273741A1
公开(公告)日：2012-11-01
申请号：US13443132
申请日：2012-04-10
申请人： Kyu-Man HWANG , Jun-Soo BAE , Sung-Un KWON , Kwang-Ho PARK
发明人： Kyu-Man HWANG , Jun-Soo BAE , Sung-Un KWON , Kwang-Ho PARK
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1683
摘要： A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.
摘要翻译：一种制造相变存储器件的方法包括：形成下电极层图案和覆盖下电极层图案的绝缘夹层，在绝缘中间层中形成第一开口以露出下电极层图案，在其上形成氧化层图案通过部分地除去氧化物层和下部电极层图案，形成绝缘层，在第一开口的侧壁和下部电极的下方形成氧化物层图案，形成绝缘层，填充第一开口的剩余部分，通过湿蚀刻工艺去除氧化物层图案以形成第二开口，并且在下电极上形成相变材料图案，使得相变材料图案填充第二开口。

3. 发明申请

US20110281428A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110281428A1
公开(公告)日：2011-11-17
申请号：US13183574
申请日：2011-07-15
申请人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
发明人： Yong-Hwan Ryu , Jun Seo , Eun-Young Kang , Jae-Seung Hwang , Sung-Un Kwon
IPC分类号： H01L21/28
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

4. 发明申请

US20080088029A1 SEMICONDUCTOR DEVICE HAVING CONTACT BARRIER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有接触障碍物的半导体器件及其制造方法
公开(公告)号：US20080088029A1
公开(公告)日：2008-04-17
申请号：US11933039
申请日：2007-10-31
申请人： Hyeong-Sun HONG , Jae-Goo LEE , Dong-Hyun KIM , Sung-Un KWON , Sang-Joon PARK , Nam-Jung KANG
发明人： Hyeong-Sun HONG , Jae-Goo LEE , Dong-Hyun KIM , Sung-Un KWON , Sang-Joon PARK , Nam-Jung KANG
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/0207 , H01L21/76802 , H01L27/10808 , H01L27/10855 , H01L27/10885 , Y10S257/905
摘要： A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.
摘要翻译：提供一种半导体器件，其具有用于具有大纵横比的绝缘触点的接触屏障，并且在相邻的导线之间具有微细的间距及其制造方法。半导体器件包括形成在两个相邻的第一导电线和两个相邻的第二导电线之间的区域中的掩埋接触。绝缘线限定埋入触点的宽度。为了形成接触屏障，形成在第二导线上的层间电介质层形成空间，并且在该空间中形成具有与层间电介质层不同的蚀刻比的绝缘线。相对于覆盖第二导线和第一绝缘线的绝缘层选择性地湿蚀刻层间电介质层以形成掩埋接触孔。埋入的接触孔填充有导电材料以形成掩埋接触。

5. 发明申请

US20060292795A1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US20060292795A1
公开(公告)日：2006-12-28
申请号：US11449848
申请日：2006-06-09
申请人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
发明人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/66825
摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
摘要翻译：在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。在衬底中形成的沟槽被转换为沟槽结构。在衬底上形成隧道氧化物层。沟槽结构之间的空间填充有第一导电层。去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。在第一导电层图案和沟槽隔离结构上形成介电层。在周边区域的基板上形成绝缘层。在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。分别在单元区域和外围区域中形成第一和第二栅极结构。

6. 发明授权

US09490256B2 Semiconductor devices having contact plugs overlapping associated bitline structures and contact holes and method of manufacturing the same 有权
标题翻译：具有与相关的位线结构和接触孔重叠的接触插塞的半导体器件及其制造方法
公开(公告)号：US09490256B2
公开(公告)日：2016-11-08
申请号：US14754040
申请日：2015-06-29
申请人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
发明人： Jun-Kyum Kim , Jung-Woo Seo , Sung-Un Kwon
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L21/76879 , H01L27/10814 , H01L27/10817 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.
摘要翻译：半导体器件可以包括根据衬底上的布局布置的多个着陆焊盘，其中每个着陆焊盘的横截面形状具有菱形形状，使得菱形形状的相对内部角度彼此相等，并且钻石形状的相邻内角彼此不相等。

7. 发明授权

US08133757B2 Method of manufacturing a phase changeable memory unit having an enhanced structure to reduce a reset current 有权
标题翻译：制造具有增强结构以减少复位电流的相变存储器单元的方法
公开(公告)号：US08133757B2
公开(公告)日：2012-03-13
申请号：US12592816
申请日：2009-12-03
申请人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
发明人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
IPC分类号： H01L29/02
CPC分类号： H01L27/2436 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.
摘要翻译：相变存储单元包括下电极，具有开口的绝缘层间结构，相变材料层和上电极。下电极形成在基板上。绝缘层间结构具有开口并且形成在下电极和基板上。开口露出下电极并且具有向下逐渐减小的宽度。相变材料层填充开口并部分地覆盖绝缘层间结构的上表面。上电极形成在相变材料层上。

8. 发明申请

US20120040508A1 Method of Forming Semiconductor Device Having Self-Aligned Plug 有权
标题翻译：形成具有自对准插头的半导体器件的方法
公开(公告)号：US20120040508A1
公开(公告)日：2012-02-16
申请号：US13188981
申请日：2011-07-22
申请人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L47/00
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译：形成基板上的导电图案。形成具有露出导电图案的开口的绝缘层。底部电极形成在导电图案和开口的第一侧壁上。在底部电极和开口的第二侧壁上形成间隔物。间隔件和底部电极形成为低于绝缘层的顶表面。数据存储插头形成在底部电极和间隔件上。数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。在数据存储插头上形成位线。

9. 发明申请

US20100144135A1 Method of manufacturing a phase changeable memory unit 有权
标题翻译：制造相变存储器单元的方法
公开(公告)号：US20100144135A1
公开(公告)日：2010-06-10
申请号：US12592816
申请日：2009-12-03
申请人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
发明人： Hyun-Suk Kwon , Young-Soo Lim , Sung-Un Kwon , Yong-Ho Ha , Jeong-Hee Park , Joon-Sang Park , Myung-Jin Kang , Doo-Hwan Park
IPC分类号： H01L21/443
CPC分类号： H01L27/2436 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer.
摘要翻译：相变存储单元包括下电极，具有开口的绝缘层间结构，相变材料层和上电极。下电极形成在基板上。绝缘层间结构具有开口并且形成在下电极和基板上。开口露出下电极并且具有向下逐渐减小的宽度。相变材料层填充开口并部分地覆盖绝缘层间结构的上表面。上电极形成在相变材料层上。

10. 发明授权

US07531450B2 Method of fabricating semiconductor device having contact hole with high aspect-ratio 有权
标题翻译：制造具有高纵横比的接触孔的半导体器件的方法
公开(公告)号：US07531450B2
公开(公告)日：2009-05-12
申请号：US11759788
申请日：2007-06-07
申请人： Yun-Seung Kang , Jun Seo , Min-Chul Chae , Jae-Seung Hwang , Sung-Un Kwon , Woo-Jin Cho
发明人： Yun-Seung Kang , Jun Seo , Min-Chul Chae , Jae-Seung Hwang , Sung-Un Kwon , Woo-Jin Cho
IPC分类号： H01L21/44
CPC分类号： H01L27/11551 , H01L21/31144 , H01L21/743 , H01L27/0688 , H01L27/11526
摘要： Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
摘要翻译：提供一种制造具有高纵横比的接触孔的半导体器件的方法。该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

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