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1. 发明授权

US06643332B1 Method and apparatus for multi-level coding of digital signals 有权
标题翻译：数字信号多级编码的方法和装置
公开(公告)号：US06643332B1
公开(公告)日：2003-11-04
申请号：US09350700
申请日：1999-07-09
申请人： Robert Morelos-Zaragoza , Shu Lin , Marc Fossorier
发明人： Robert Morelos-Zaragoza , Shu Lin , Marc Fossorier
IPC分类号： H04L2302
CPC分类号： H04L1/006 , H04L1/0054 , H04L1/0068 , H04L25/4917 , H04L27/345
摘要： A method and apparatus for multi-level encrypted encoding and decoding of digital signals, which includes utilizing only one type of encoder and one type of decoder. This can be either the same encoder and decoder used in throughout the process, or multiple, identical encoders and decoders. This allows the system to compensate for atmospheric degradation with higher bandwidth efficiency and a simplified receiver structure. The invention further identifies a 2j symbol generation technique that maps in disjoint regions of X-dimensional space, which allows different data bits to be eliminated from the decoding scheme and maximizes the number of independent data substreams that can be maintained.
摘要翻译：一种用于数字信号的多级加密编码和解码的方法和装置，其包括仅使用一种类型的编码器和一种类型的解码器。这可以是整个过程中使用的编码器和解码器，或多个相同的编码器和解码器。这允许系统以更高的带宽效率和简化的接收机结构来补偿大气劣化。本发明还识别了在X维空间的不相交区域中映射的2j符号生成技术，其允许从解码方案中消除不同的数据位，并使可维护的独立数据子流的数量最大化。

2. 发明授权

US6138265A Decoding trellis coded modulated data with a conventional Viterbi decoder 失效
标题翻译：用传统的维特比解码器解码网格编码调制数据
公开(公告)号：US6138265A
公开(公告)日：2000-10-24
申请号：US100510
申请日：1998-06-19
申请人： Robert Morelos-Zaragoza , Advait Mogre , Cheng Qian , Rajesh Juluri
发明人： Robert Morelos-Zaragoza , Advait Mogre , Cheng Qian , Rajesh Juluri
IPC分类号： H03M13/00 , H03M13/23 , H03M13/25 , H03M13/41 , H04L1/00 , H03M13/03
CPC分类号： H03M13/6325 , H03M13/23 , H03M13/25 , H03M13/41 , H04L1/0052 , H04L1/0054 , H04L1/006 , H04L27/34 , H04L1/0068
摘要： The present invention performs decoding of trellis coded modulated data using a conventional decoder by splitting up the tasks of estimating the uncoded portion and estimating the coded portion into separate tasks. The task of estimating the coded portion is performed based on a transformation on the input symbols and by taking advantage of the symmetry of the constellation associated with the modulated data when referencing a lookup table. The lookup table may also be designed to be smaller than a straight forward implementation by taking advantage of the same symmetry of the constellation.The alteration of the data is then corrected for, resulting in a smaller constellation (Bi Phase Shift Key for 1 coded bit per symbol systems, Quadrature Phase Shift Key for 2 coded bits per symbol systems) mapping only the coded portion of the data. This allows a conventional Viterbi decoder to estimate the coded portion. The task of estimating the uncoded portion of the data is then performed by using information about the sector of the constellation of the original data along with a re-encoded version of the estimated coded portion.
摘要翻译：本发明通过分解估计未编码部分的任务并将编码部分估计为分离的任务，使用常规解码器来执行网格编码调制数据的解码。基于对输入符号的变换，并且在引用查找表时利用与调制数据相关联的星座的对称性来执行估计编码部分的任务。也可以通过利用星座的相同对称性将查找表设计为小于直接实现。然后校正数据的改变，导致较小的星座（仅用于符号系统的1个编码比特的Bi相位移键，每符号系统的2个编码比特的正交相移键）仅映射数据的编码部分。这允许常规维特比解码器估计编码部分。然后通过使用关于原始数据的星座的扇区的信息以及估计的编码部分的重新编码版本来执行估计数据的未编码部分的任务。

3. 发明授权

US6081920A Method and apparatus for fast decoding of a Reed-Solomon code 失效
标题翻译：用于快速解码里德 - 所罗门码的方法和装置
公开(公告)号：US6081920A
公开(公告)日：2000-06-27
申请号：US4748
申请日：1998-01-08
申请人： Robert Morelos-Zaragoza
发明人： Robert Morelos-Zaragoza
IPC分类号： H03M13/15 , H03M13/00
CPC分类号： H03M13/15
摘要： A method and apparatus for fast decoding of a Reed-Solomon codeword which includes storing the codeword in memory, finding syndromes of the codeword, using the syndromes to determine the number of errors in the codeword, which in turn are used to find an error locator polynomial for the codeword, which is a polynomial whose roots can be used to find the locations of the errors. This error locator polynomial is then be used to find the positions of the errors in the codeword. The positions of the errors in the codeword can be used along with the syndromes to determine the values of the errors in the codeword.
摘要翻译：一种用于对Reed-Solomon码字进行快速解码的方法和装置，其包括将码字存储在存储器中，使用该校正子来确定码字的校正子，以确定码字中的错误数目，这又用于找到误差定位器用于码字的多项式，其是其根可以用于找到错误位置的多项式。然后使用该误差定位多项式来查找码字中的错误的位置。可以将码字中的错误的位置与校正子一起使用以确定码字中的错误的值。

4. 发明授权

US06487692B1 Reed-Solomon decoder 有权
标题翻译：里德 - 所罗门解码器
公开(公告)号：US06487692B1
公开(公告)日：2002-11-26
申请号：US09468577
申请日：1999-12-21
申请人： Robert Morelos-Zaragoza
发明人： Robert Morelos-Zaragoza
IPC分类号： H03M1315
CPC分类号： H03M13/1525 , H03M13/25 , H03M13/41
摘要： A Reed-Solomon decoder capable of correcting two symbol errors in a codeword of a Reed-Solomon RS(128,122,7) code over a Galois field GF(128) is provided. In an exemplary embodiment, the Reed-Solomon decoder is suitable for use in cable modems with little or no loss in error performance over Reed-Solomon decoder correcting three errors in a codeword.
摘要翻译：提供了能够在伽罗瓦域GF（128）上校正Reed-Solomon RS（128,122,7）码的码字中的两个码元错误的里德 - 所罗门解码器。在示例性实施例中，Reed-Solomon解码器适用于在Reed-Solomon解码器中对码字中的三个错误进行校正的误差性能很少或没有损失的电缆调制解调器。

5. 发明授权

US6101626A Method for choosing coding schemes, mappings, and puncturing rates for modulations/encoding systems 失效
标题翻译：用于选择调制/编码系统的编码方案，映射和打孔速率的方法
公开(公告)号：US6101626A
公开(公告)日：2000-08-08
申请号：US18678
申请日：1998-02-04
申请人： Robert Morelos-Zaragoza , Advait M. Mogre
发明人： Robert Morelos-Zaragoza , Advait M. Mogre
IPC分类号： H03M13/00 , H03M13/23 , H03M13/25 , H03M13/41 , H04L1/00 , H03M13/03
CPC分类号： H04L1/006 , H03M13/23 , H03M13/25 , H03M13/41 , H03M13/6325 , H04L1/0052 , H04L1/0054 , H04L27/34 , H04L1/0068
摘要： The purpose of the present invention is to provide a method for choosing the coding schemes, mappings, and puncturing rates for a modulation/demodulation system which would allow the system to compensate for certain transformations of the code in a post-Viterbi step as opposed to pre-Viterbi. This would allow for faster and simpler decoding of a code. The method includes the steps of: choosing a coding scheme and puncturing rate; determining a code generator matrix using said coding scheme and puncturing rate; multiplying the code generator matrix by the transformation matrix by the code generator matrix's feedback free right inverse and seeing if the outcome is equal to the code generator matrix multiplied by the transform matrix; multiplying the error matrix by the code generator matrix's feedback free right inverse by the code generator matrix and seeing if the outcome is equal to the error matrix; repeating all the steps until a code generator matrix that satisfies said invariancy equations is found; and choosing a mapping scheme that takes advantage of the invariancy.
摘要翻译：本发明的目的是提供一种用于选择调制/解调系统的编码方案，映射和打孔速率的方法，该方法将允许系统在后维特比步骤中补偿代码的某些变换，而不是维特比之前。这将允许对代码进行更快更简单的解码。该方法包括以下步骤：选择编码方案和打孔率; 使用所述编码方案和打孔率来确定代码生成器矩阵; 将代码生成矩阵乘以代码生成矩阵的反馈自由权反转，并且查看结果是否等于乘以变换矩阵的代码生成矩阵; 通过代码生成器矩阵将代码生成矩阵的反馈自由逆乘乘误差矩阵，并查看结果是否等于误差矩阵; 重复所有步骤，直到找到满足所述不变方程的代码生成器矩阵; 并选择利用不间断的映射方案。

6. 发明授权

US07065149B2 Transmitter, the method of the same and communication system 失效
公开(公告)号：US07065149B2
公开(公告)日：2006-06-20
申请号：US10184688
申请日：2002-06-27
申请人： Mohammad Ghavami , Robert Morelos-Zaragoza
发明人： Mohammad Ghavami , Robert Morelos-Zaragoza
IPC分类号： H04B7/02 , H04L1/02
CPC分类号： H04L1/0625 , H04B7/0617
摘要： A transmitter, the method of the same, and a communication system using the scheme of space-time block coding employing the multiple beams to mitigate the multipath fading. A transmitter constituted array antennas first performs beams scanning employing beamforming network for estimating the channel space gain pattern, then estimates number of the beams for transmission and the corresponding angles of each beam, performs beam space-time block encoding of input signals then transmitting the encoded signals. The receiver receives the signal and performs linear channel decoding, for example, maximum likelihood decoding.

7. 发明授权

US06804309B1 Modulation format identification device and method of same 失效
标题翻译：调制格式识别装置及其方法
公开(公告)号：US06804309B1
公开(公告)日：2004-10-12
申请号：US09697539
申请日：2000-10-26
申请人： Robert Morelos-Zaragoza
发明人： Robert Morelos-Zaragoza
IPC分类号： H04L2722
CPC分类号： H04L27/0012
摘要： A modulation format identification device capable of realizing a practical receiver capable of identifying a modulation format of a received signal irrespective of its modulation format by a simple configuration, wherein provision is made of a phase lock detector group having a plurality of detectors provided corresponding to a plurality of modulation formats and with the received signals input in parallel thereto, counting a number of symbols in accordance with the modulation format for every detector, making a primary decision that the received signal has been modulated by the related modulation format when the count exceeds a constant threshold value, and outputting the results as lock detection flags and a logic circuit for exclusively selecting one modulation format upon receipt of the plurality of output results of the phase lock detector group, and a method of the same.
摘要翻译：一种调制格式识别装置，其能够实现能够通过简单配置来识别接收信号的调制格式的实际接收机，而不管其调制格式如何，其中提供了一种相位锁定检测器组，其具有对应于多个调制格式和与其并行输入的接收信号，根据每个检测器的调制格式对多个符号进行计数，当计数超过一个时，作出主要判定，即接收信号已被相关调制格式调制并将该结果输出为锁定检测标志，以及用于在接收到锁相检测器组的多个输出结果时专门选择一个调制格式的逻辑电路及其方法。

8. 发明授权

US06751770B2 Decoder for iterative decoding of binary cyclic codes 失效
标题翻译：用于二进制循环码迭代解码的解码器
公开(公告)号：US06751770B2
公开(公告)日：2004-06-15
申请号：US09974675
申请日：2001-10-10
申请人： Robert Morelos-Zaragoza
发明人： Robert Morelos-Zaragoza
IPC分类号： H03M1300
CPC分类号： H03M13/6594 , H03M13/1102 , H03M13/1131 , H03M13/1134 , H03M13/1191 , H03M13/15 , H03M13/152 , H03M13/19 , H03M13/3723
摘要： A decoder for performing soft decision iterative decoding of a cyclic code based on belief propagation, includes an information exchange control unit, an X processor, and a Z processor. The information exchange control unit takes &pgr;x-metrics that were calculated by the X processor for nonzero elements in each of n-cyclic shifts of the parity-check polynomial of the code, and distributes the &pgr;x-metrics to the Z processor as the &pgr;z-metrics for a corresponding check node. The information exchange control unit takes &lgr;z-metrics that were calculated by the Z processor for nonzero elements in each of n-cyclic shifts in a reverse order of the parity-check polynomial, and distributes them to the X processor as &lgr;x-metrics for the corresponding code node. The operation of the information exchange control unit can be represented by the Tanner graph associated with an extended parity-check matrix, which is produced by adding k rows to the parity-check matrix of the cyclic code.
摘要翻译：用于基于置信度传播执行循环码的软判决迭代解码的解码器包括信息交换控制单元，X处理器和Z处理器。信息交换控制单元在代码的奇偶校验多项式的n个循环移位中的每一个中采用由X处理器计算的非零元素的像素度量，并将像素度量分配给Z处理器作为比特 - 相应检查节点的度量。信息交换控制单元以奇偶校验多项式的相反顺序，采用由Z处理器计算的非零元素的n个循环移位中的非零元素，并将其分配给X处理器，作为lambdax度量相应的代码节点。信息交换控制单元的操作可以由与扩展奇偶校验矩阵相关联的Tanner图表示，该扩展奇偶校验矩阵是通过将k行加到循环码的奇偶校验矩阵而产生的。

9. 发明授权

US06768337B2 Integrated circuit, method of circuit configuration and program thereof 失效
标题翻译：集成电路，电路配置方法及程序
公开(公告)号：US06768337B2
公开(公告)日：2004-07-27
申请号：US10223543
申请日：2002-08-19
申请人： Ryuji Kohno , Kenichiro Akai , Yukitoshi Sanada , Robert Morelos-Zaragoza , Lachlan Michael
发明人： Ryuji Kohno , Kenichiro Akai , Yukitoshi Sanada , Robert Morelos-Zaragoza , Lachlan Michael
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , G06F17/5054 , H03K19/17768
摘要： A plurality of circuit cells, a plurality of matrix switch sections and a plurality of switch sections for connecting between the plurality of circuit cells, all of which form a part of a circuit cell array, and a plurality of input/output cell sections arranged around the circuit cell array all change their circuit configurations in accordance with a configuration data to be supplied. In some of these circuit blocks, at least a part of the circuit thereof is fixed at a predetermined circuit configuration, and a conversion of the configuration data based on proprietary information regarding the fixed circuit is performed at a supplier of the configuration data. Thus, a differential configuration data for portions of the circuit other than the fixed circuit portion is generated and supplied to the integrated circuit.
摘要翻译：多个电路单元，多个矩阵开关部分和用于连接多个电路单元之间的多个开关部分，所有这些电路单元都构成电路单元阵列的一部分，以及多个输入/输出单元部分电路单元阵列根据要提供的配置数据全部改变其电路配置。在这些电路块的一些中，其电路的至少一部分被固定为预定的电路配置，并且在配置数据的供应商处执行基于关于固定电路的专有信息的配置数据的转换。因此，生成除了固定电路部分之外的电路的部分的差分配置数据并将其提供给集成电路。

10. 发明授权

US6134696A Encoding and decoding rate-1/n convolutional codes and their punctured versions 失效
标题翻译：编码和解码速率-1 / n卷积码及其穿孔版本
公开(公告)号：US6134696A
公开(公告)日：2000-10-17
申请号：US87459
申请日：1998-05-28
申请人： Robert Morelos-Zaragoza , Advait Mogre
发明人： Robert Morelos-Zaragoza , Advait Mogre
IPC分类号： H03M13/00 , H03M13/23 , H03M13/03
CPC分类号： H03M13/23
摘要： The present invention is directed to the encoding and decoding of a digital signal. The encoding process results in a rate-1/n convolutional code derived from a rate-1/2 convolutional code. The process includes: selecting a base convolutional encoding rate of rate-1/l, where l is an integer; selecting an output encoding rate of 1/n, where n is an integer greater than 1; encoding an input digital signal into a convolutional code comprised of signals S(0) through S(l-1), the convolutional code having the rate 1/l convolutional code encoding rate; and providing a rate-1/n convolutional code, which is derived from the rate-1/l convolutional code, the rate-1/n convolutional code having N(i) copies of the rate-1/l signals S(i), where i is from 0 through 1-l and where the sum of N(i) is equal to n. The decoding process results in a digital signal estimated from received symbols which include rate-1/n convolutional code generated by the above encoding process and any noise that may have been introduced by a transmission medium. The process includes the step of: generating a signal pair from the received symbols, the signal pair having a first signal and a second signal which are suitable for decoding by a rate-1/2 convolutional decoder. The first signal is an average of a sum of encoded signals which correspond to positions in the rate-1/2 convolutional code encoded using a first generator polynomial. The second signal is an average of a sum of encoded signals which correspond to positions in the rate-1/n convolutional code encoded using a second generator polynomial. The method also includes a step of decoding the signal pairs using a rate-1/2 convolutional decoder.
摘要翻译：本发明涉及数字信号的编码和解码。编码过程导致从速率-1 / 2卷积码导出的速率-1 / n卷积码。该过程包括：选择速率-1 / l的基本卷积编码速率，其中l是整数; 选择1 / n的输出编码率，其中n是大于1的整数; 将输入数字信号编码为由信号S（0）至S（1-1）组成的卷积码，卷积码具有速率1/1卷积码编码率; 并且提供从速率-1 / l卷积码导出的速率-1 / n卷积码，具有速率-1 / l信号S（i）的N（i）个拷贝的速率-1 / n卷积码，，其中i是从0到1-l，并且其中N（i）的和等于n。解码处理产生从包括由上述编码处理产生的速率-1 / n卷积码和可能由传输介质引入的任何噪声的接收符号估计的数字信号。该过程包括以下步骤：从接收的符号生成信号对，信号对具有适合于通过速率1/2卷积解码器解码的第一信号和第二信号。第一信号是对应于使用第一生成多项式编码的速率-1 / 2卷积码中的位置的编码信号的和的平均值。第二信号是对应于使用第二生成多项式编码的速率-1 / n卷积码中的位置的编码信号的和的平均值。该方法还包括使用速率-1 / 2卷积解码器对信号对进行解码的步骤。

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