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1. 发明授权

US08384210B1 Thermal interface material and semiconductor component including the thermal interface material 有权
标题翻译：热界面材料和包括热界面材料的半导体组件
公开(公告)号：US08384210B1
公开(公告)日：2013-02-26
申请号：US11147598
申请日：2005-06-07
申请人： Richard C. Blish, II , James L. Hayward
发明人： Richard C. Blish, II , James L. Hayward
IPC分类号： H01L23/34
CPC分类号： H01L23/42 , H01L23/10 , H01L23/3736 , H01L23/49816 , H01L2224/16225 , H01L2224/73253 , H01L2924/15311
摘要： A thermal interface material for use in manufacturing a semiconductor component and a method for manufacturing the semiconductor component. The thermal interface material includes a metallic element in combination with either antimony or tin. Suitable metallic elements include gallium or indium. The concentration of antimony or tin is about 2 percent or less by weight of the thermal interface material. A semiconductor chip is mounted to a support substrate and the thermal interface material is disposed on the semiconductor chip. A lid or a heatsink is coupled to the semiconductor chip via the thermal interface material.
摘要翻译：一种用于制造半导体部件的热界面材料及其制造方法。热界面材料包括与锑或锡组合的金属元素。合适的金属元素包括镓或铟。锑或锡的浓度约为热界面材料重量的2％或更少。半导体芯片安装在支撑基板上，热界面材料设置在半导体芯片上。盖子或散热器经由热界面材料耦合到半导体芯片。

2. 发明授权

US06803653B1 Apparatus for suppressing packaged semiconductor chip curvature while minimizing thermal impedance and maximizing speed/reliability 有权
标题翻译：用于抑制封装的半导体芯片曲率同时最小化热阻抗并使速度/可靠性最大化的装置
公开(公告)号：US06803653B1
公开(公告)日：2004-10-12
申请号：US10010392
申请日：2001-12-07
申请人： Robert E. Likins , Richard C. Blish, II , Sharad M. Shah , Sidharth Sidharth , Devendra Natekar
发明人： Robert E. Likins , Richard C. Blish, II , Sharad M. Shah , Sidharth Sidharth , Devendra Natekar
IPC分类号： H01L2334
CPC分类号： H01L23/36 , H01L23/42 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01322 , H01L2924/10253 , H01L2924/12044 , H01L2924/3011 , H01L2924/3511 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor structure includes a substrate and a semiconductor devices secured to the substrate. A stabilizing member is secured to the semiconductor device, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the substrate. The bending stiffness of the substrate is substantially the same as the bending stiffness of the stabilizing member, wherein: bending stiffness=Et3, with E=Young's modulus, and t=thickness. In another embodiment, a stabilizing member is secured to the substrate, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the die. The bending stiffness of the die is substantially the same as the bending stiffness of the stabilizing member, with bending stiffness defined as above.
摘要翻译：半导体结构包括衬底和固定到衬底的半导体器件。稳定构件被固定到半导体器件，并且具有基本上与衬底的热膨胀系数相同的热膨胀系数。基板的弯曲刚度基本上与稳定构件的弯曲刚度相同，其中：在另一个实施例中，稳定构件固定到基板上，并且具有与系数相同的热膨胀系数模具的热膨胀。模具的弯曲刚度基本上与稳定构件的弯曲刚度相同，具有如上所述的弯曲刚度。

3. 发明授权

US06429657B1 Apparatus for improving image depth resolution in a magnetic field imaging apparatus 失效
标题翻译：用于改善磁场成像装置中的图像深度分辨率的装置
公开(公告)号：US06429657B1
公开(公告)日：2002-08-06
申请号：US09757116
申请日：2001-01-09
申请人： Richard C. Blish, II
发明人： Richard C. Blish, II
IPC分类号： G01V300
CPC分类号： G01V3/081
摘要： A magnetic field imaging apparatus for sensing a magnetic field generated by current flowing in the semiconductor device includes a pair of sensing devices which may be focused at a chosen depth in a semiconductor device. The sensing devices may be movable so that they may be focused at different focal points. The apparatus may also include three or more sensing devices, which can be chosen to operate in tears to define a variety of focus depths in a semiconductor device.
摘要翻译：用于感测由在半导体器件中流动的电流产生的磁场的磁场成像装置包括可以在半导体器件中以选定深度聚焦的一对感测装置。感测装置可以是可移动的，使得它们可以在不同的焦点处聚焦。该装置还可以包括三个或更多个感测装置，其可被选择为在半导体装置中限定多种聚焦深度的撕裂。

4. 发明授权

US06320400B1 Method and system for selectively disconnecting a redundant power distribution network to indentify a site of a short 有权
标题翻译：用于选择性地断开冗余配电网以识别短路站点的方法和系统
公开(公告)号：US06320400B1
公开(公告)日：2001-11-20
申请号：US09208713
申请日：1998-12-09
申请人： J. Courtney Black , Richard C. Blish, II , Mehrdad Mahanpour , Mohammad Massoodi , S. Sidharth
发明人： J. Courtney Black , Richard C. Blish, II , Mehrdad Mahanpour , Mohammad Massoodi , S. Sidharth
IPC分类号： G01R3102
CPC分类号： G01R31/316 , G01R31/31721
摘要： A system and method for identifying a location of a short in a circuit of a semiconductor device is disclosed. The method and system includes providing a power supply and providing a power distribution network coupled to the power supply. The power distribution network is for distributing power to a portion of the circuit. The power distribution network further including means for selectively disconnecting a portion of the power distribution network. The portion of the power distribution network supplies power to the location of the short.
摘要翻译：公开了一种用于识别半导体器件的电路中的短路的位置的系统和方法。该方法和系统包括提供电源并提供耦合到电源的配电网络。配电网络用于将电力分配给电路的一部分。配电网络还包括用于选择性地断开配电网络的一部分的装置。配电网的一部分为短路的位置供电。

5. 发明授权

US06285181B1 Method and system for determining the location of an open circuit in a semiconductor device using power modulation 失效
标题翻译：用于使用功率调制确定半导体器件中的开路位置的方法和系统
公开(公告)号：US06285181B1
公开(公告)日：2001-09-04
申请号：US09177759
申请日：1998-10-23
申请人： Richard C. Blish, II
发明人： Richard C. Blish, II
IPC分类号： G01R3128
CPC分类号： G01R31/307
摘要： A system and method for detecting a location of an open circuit is disclosed. The open circuit is in a circuit of semiconductor device. The semiconductor device has a surface. The method and system include supplying alternating power to the semiconductor device and sensing a time-varying signal that is related to the alternating power. The method and system also include determining where the signal is substantially changed.
摘要翻译：公开了一种用于检测开路位置的系统和方法。开路在半导体器件的电路中。半导体器件具有表面。该方法和系统包括向半导体器件提供交流电力并感测与交流功率相关的时变信号。该方法和系统还包括确定信号在何处显着改变。

6. 发明授权

US6046507A Electrophoretic coating methodology to improve internal package delamination and wire bond reliability 失效
标题翻译：电泳涂层方法，以提高内包装分层和丝焊可靠性
公开(公告)号：US6046507A
公开(公告)日：2000-04-04
申请号：US986087
申请日：1997-12-08
申请人： Colin D. Hatchard , Richard C. Blish, II
发明人： Colin D. Hatchard , Richard C. Blish, II
IPC分类号： H01L21/56 , H01L23/31 , H01L23/48
CPC分类号： H01L23/3135 , H01L21/56 , H01L2224/05599 , H01L2224/48091 , H01L2224/48247 , H01L2224/85399 , H01L2224/8592 , H01L24/48 , H01L2924/00014 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/181
摘要： Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The principles of the present invention contemplate electrostatically depositing an exceptionally uniform coating on electronic components, especially microchips, and more especially still, on integrated circuits prior to the encapsulation of the electronic components into plastic-packaged components. The coating, for instance applied to a completed leadframe assembly, including die and wire bonds, serves two purposes. It improves adhesion of the molding compound forming the package, thereby reducing the chances for delamination of the package. The coating also isolates the relatively fragile wire bonds, including their attachment points to the chip and the bonding pads and the leads, from chemical and metallurgical attack by the flame retardant found in many molding compounds.
摘要翻译：用于实现电子部件的多相塑料封装的方法，以及根据该方法制造的封装的电子部件。本发明的原理考虑在将电子部件封装到塑料封装的部件之前，将静电沉积在电子部件，特别是微芯片上，特别是在集成电路上静电沉积。涂层，例如应用于完整的引线框架组件，包括管芯和引线接合，用于两个目的。它改善了形成包装的模塑料的粘合性，从而降低了包装分层的可能性。该涂层还将相对脆弱的引线键合（包括它们的连接点）分离到芯片和接合焊盘和引线上，在许多模制化合物中发现的阻燃剂进行化学和冶金攻击。

7. 发明授权

US6037547A Via configuration with decreased pitch and/or increased routing space 失效
标题翻译：通过配置减少音调和/或增加路由空间
公开(公告)号：US6037547A
公开(公告)日：2000-03-14
申请号：US984224
申请日：1997-12-03
申请人： Richard C. Blish, II
发明人： Richard C. Blish, II
IPC分类号： H05K1/11 , H05K1/00
CPC分类号： H05K1/115 , H05K1/113 , H05K2201/09227 , H05K2201/09854 , H05K2201/10734 , Y10T29/49165
摘要： A number of non-circular vias are defined in a printed wiring board layer. The vias are preferably elliptical, with their long dimensions oriented at an angle to the primary axes of the via or grid array. By providing elongated, non-circular vias, it is possible to decrease the pitch of the via array, or provide improved routing of escape traces.
摘要翻译：在印刷电路板层中限定了许多非圆形通孔。通孔优选为椭圆形，其长尺寸与通孔或栅格阵列的主轴成一定角度。通过提供细长的非圆形通孔，可以减小通孔阵列的间距，或提供改进的逃生轨迹布线。

8. 发明授权

US6021074A Direct access to random redundant logic gates by using multiple short addresses 失效
标题翻译：通过使用多个短地址直接访问随机冗余逻辑门
公开(公告)号：US6021074A
公开(公告)日：2000-02-01
申请号：US148684
申请日：1998-09-04
申请人： Richard C. Blish, II
发明人： Richard C. Blish, II
IPC分类号： G01R31/3185 , G11C7/10 , G11C7/18 , G11C8/12 , G11C7/00
CPC分类号： G01R31/318516 , G11C7/1006 , G11C7/18 , G11C8/12
摘要： The present invention provides a method for accessing a plurality of gates in a random logic structure. The method includes the steps of providing a first address for a first line coupled to a gate, providing a second address for a second line coupled to the gate, providing at least one additional address for at least one additional line coupled to the gate, and accessing the gate at the intersection of the first, second, and additional addresses. A method for accessing random logic gates which allows for the testing of more logic gates than conventional methods and which is also faster than conventional methods has been disclosed. The method of the present invention provides a three or more dimensional (segmented) address for each gate which allows for the status of more gates to be specifically ascertained. This allows for more ease in testing, saving valuable time. The method of the present invention also has the added advantage of allowing repair of defective gates with redundant gates.
摘要翻译：本发明提供一种以随机逻辑结构访问多个门的方法。该方法包括以下步骤：提供耦合到门的第一线的第一地址，为耦合到门的第二线提供第二地址，为耦合到门的至少一个附加线提供至少一个附加地址，以及在第一，第二和附加地址的交点处访问门。已经公开了一种访问随机逻辑门的方法，其允许比常规方法更多的逻辑门的测试，并且其也比传统方法更快。本发明的方法为每个门提供三维或更多维（分段）地址，其允许具体确定更多门的状态。这样可以更方便地进行测试，节省宝贵的时间。本发明的方法还具有允许用冗余门修复缺陷门的附加优点。

9. 发明授权

US07253504B1 Integrated circuit package and method 有权
标题翻译：集成电路封装及方法
公开(公告)号：US07253504B1
公开(公告)日：2007-08-07
申请号：US11010784
申请日：2004-12-13
申请人： Jun Zhai , Jinsu Kwon , Richard C. Blish, II
发明人： Jun Zhai , Jinsu Kwon , Richard C. Blish, II
IPC分类号： H01L23/48 , H01L23/12 , H05K1/11 , H01R12/04
CPC分类号： H05K3/4641 , H01L21/563 , H01L23/49822 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01078 , H01L2924/01087 , H01L2924/3025 , H05K1/0271 , H05K2201/0352 , H05K2201/068 , H01L2924/00
摘要： An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configured to resist warpage of the integrated circuit package, the layer provided a distance from the central axis.
摘要翻译：集成电路封装包括具有将基板划分为上半部和下半部的中心轴以及耦合到基板的集成电路的基板。在其下半部分中的衬底内设置有层，其被配置为抵抗集成电路封装的翘曲，该层与中心轴线设置一段距离。

10. 发明授权

US07157131B1 Prevention of counterfeit markings on semiconductor devices 有权
标题翻译：防止半导体器件上的伪造标记
公开(公告)号：US07157131B1
公开(公告)日：2007-01-02
申请号：US10212950
申请日：2002-08-06
申请人： Richard C. Blish, II , John James Slevin
发明人： Richard C. Blish, II , John James Slevin
IPC分类号： B32B3/24 , B29C35/08 , G01R31/26 , H01L23/29
CPC分类号： H01L23/544 , H01L23/573 , H01L2924/0002 , Y10S264/916 , Y10T428/24322 , Y10T428/24331 , H01L2924/00
摘要： A lidded semiconductor device has a first layer applied to the lid, which first layer is chosen of a material which fluoresces upon application of non-visible electromagnetic waves thereto, for example, ultraviolet light. A second layer is provided over the first layer. Openings extend through the second layer and further extend to a substantial depth into the first layer, for example, generally halfway into the first layer, to expose portions of the first layer.
摘要翻译：带盖的半导体器件具有施加到盖的第一层，该第一层选自在对其施加不可见的电磁波（例如紫外光）时发荧光的材料。在第一层上提供第二层。开口延伸穿过第二层并且进一步延伸到第一层的大部分深度，例如大体中途进入第一层，以暴露第一层的部分。

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