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1. 发明申请

WO2011161202A3 A PARALLEL MULTI-PIPELINE SYSTOLIC ARRAY FOR COMPLEX SINGULAR VALUE DECOMPOSITION ON A MULTI-PROCESSOR DEVICE 审中-公开
标题翻译：用于多处理器设备上的复杂单值分解的并行多管道同步阵列
公开(公告)号：WO2011161202A3
公开(公告)日：2013-01-17
申请号：PCT/EP2011060527
申请日：2011-06-22
申请人： INTRACOM S A TELECOM SOLUTIONS , DIMITRIOU ATHANASIOS , PERISSAKIS STYLIANOS , PANAYIOTOPOULOS ILIAS
发明人： DIMITRIOU ATHANASIOS , PERISSAKIS STYLIANOS , PANAYIOTOPOULOS ILIAS
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： The present invention refers to the field of wireless communications and more specifically to the design of a Parallel Multi-Pipeline Systolic Array (PMSA) architecture that implements Complex Singular Value Decomposition (CSVD) on a multi-processor device. CSVD is an important matrix factorization technique of a complex matrix P into a product of three matrices, i.e. a Hermitian unitary matrix of eigenvectors U, a diagonal matrix of eigenvalues S and a matrix of eigenvectors V, with several applications in Digital signal processing and wireless communications. The apparatus to perform the CSVD includes n sets of blocks, with n being a multiple of three, with each set of blocks comprising a first hardware block (60, 13), a second hardware block (70, 14) other than the first hardware block and a third hardware block (15) other than the first hardware block and the second hardware block; whereby a) the first hardware block (60, 13) of each of the n sets of blocks includes means to transform a 2x2 square matrix to a 2x2 upper triangular square matrix, b) the second hardware block (70, 14) of each of the n sets of blocks includes means to transform a 2x2 upper triangular matrix to a to a 2x2 diagonal square matrix c) the third hardware block (15) of each of the n sets of blocks includes means to swap and exchange elements of matrices. Further the apparatus includes means to transmit the output of the i-th set of blocks, with i equals 1 to n-1, to the i+1 set of blocks, and means to process a plurality of consecutive matrices simultaneously.
摘要翻译：本发明涉及无线通信领域，更具体地，涉及在多处理器设备上实现复杂奇异值分解（CSVD）的并行多管线收缩阵列（PMSA）架构的设计。 CSVD是复矩阵P成为三个矩阵的乘积的重要矩阵分解技术，即特征向量U的Hermitian酉矩阵，特征值S的对角矩阵和特征向量V的矩阵，在数字信号处理和无线通信。执行CSVD的装置包括n组块，其中n是3的倍数，每组块包括第一硬件块（60,13），除第一硬件（60,13）之外的第二硬件块（70,14）块和除第一硬件块和第二硬件块之外的第三硬件块（15）; 由此a）n组块中的每一个的第一硬件块（60,13）包括将2x2正方形矩阵变换为2x2上三角形矩形矩阵的装置，b）每个块的第二硬件块（70,14） n组块包括将2x2上三角矩阵变换为2×2对角方矩阵的装置c）n组块中的每一个的第三硬块（15）包括交换和交换矩阵元素的装置。此外，该装置包括将i个等于1到n-1的第i组块的输出传送到第i + 1个块的装置，以及同时处理多个连续矩阵的装置。

2. 发明申请

WO2011038940A1 MATRIX INVERSION USING QR DECOMPOSITION ON A PARALLEL PIPELINED SYSTOLIC ARRAY 审中-公开
标题翻译：使用QR分解在并行管道同步阵列上的矩阵反演
公开(公告)号：WO2011038940A1
公开(公告)日：2011-04-07
申请号：PCT/EP2010/051094
申请日：2010-01-29
申请人： INTRACOM S.A. TELECOM SOLUTIONS , DIMITRIOU, Athanasios , PANAYIOTOPOULOS, Ilias , PERISSAKIS, Stylianos
发明人： DIMITRIOU, Athanasios , PANAYIOTOPOULOS, Ilias , PERISSAKIS, Stylianos
IPC分类号： H04L25/02 , G06F15/80 , G06F17/16
CPC分类号： H04L25/0242 , G06F17/16
摘要： The present invention refers to the field of wireless communications and more specifically to the design of a Parallel Pipelined Systolic Array (PPSA) architecture that implements a Multiple Input Multiple Output (MIMO) zero- forcing detector. In particular the invention refers to a systolic array architecture that implements QR decomposition (QRD), i.e. a method for performing matrix inversion and an apparatus to implement such a method on one or a plurality of consecutive matrices. The invention also refers to a receiving apparatus for Multiple Input Multiple Output transmission of an OFDMA symbol. An apparatus for QR decomposition of one or a plurality of consecutive matrices H( k ) with at least four columns to a plurality of consecutive corresponding upper triangular matrices R( k ) and unitary matrices Q H ( k ) according to the invention comprises at least four pipeline branches, whereby a) each one of the four pipeline branches implements a systolic array structure to process one of the at least four columns of the H( k ) consecutive matrices and b) at least two of the at least four systolic array structures are different. A method for QR decomposition of a matrix H with at least four columns to an upper triangular R matrix and a unitary Q H matrix according to the invention, employes at least four systolic array pipeline branches that form a parallel pipelined systolic array architecture, whereby each one of the at least four columns of the H matrix is processed by one of the at least four systolic array pipeline branches, the at least four columns of the H matrix are processed in parallel by the at least four systolic array pipeline branches, and at least two of the at least four systolic array pipeline branches have a different structure.
摘要翻译：本发明涉及无线通信领域，更具体地涉及实现多输入多输出（MIMO）零强制检测器的并行流水线收缩阵列（PPSA）架构的设计。具体地，本发明涉及实现QR分解（QRD）的收缩阵列结构，即用于执行矩阵反演的方法和在一个或多个连续矩阵上实现这种方法的装置。本发明还涉及用于OFDMA符号的多输入多输出传输的接收装置。根据本发明的用于具有至少四列的一个或多个连续矩阵H（k）与多个连续对应的上三角矩阵R（k）和酉矩阵QH（k）的QR分解的装置包括至少四个流水线分支，其中a）四个流水线分支中的每一个实现收缩阵列结构以处理所述H（k）个连续矩阵的所述至少四列中的一个;以及b）所述至少四个所述收缩阵列结构中的至少两个不同。根据本发明的用于具有至少四列的矩阵H与上三角形R矩阵和单一QH矩阵的QR分解的方法采用形成平行流水线收缩阵列架构的至少四个收缩阵列管线分支，其中每个所述H矩阵的所述至少四列的所述至少四列通过所述至少四个收缩阵列管线分支中的一个进行处理，所述H矩阵的所述至少四列由所述至少四个收缩阵列管线分支并行处理，并且至少至少四个收缩阵列管线分支中的两个具有不同的结构。

3. 发明申请

WO2011161202A2 A PARALLEL MULTI-PIPELINE SYSTOLIC ARRAY FOR COMPLEX SINGULAR VALUE DECOMPOSITION ON A MULTI-PROCESSOR DEVICE 审中-公开
标题翻译：用于多处理器设备上的复杂单值分解的并行多管道同步阵列
公开(公告)号：WO2011161202A2
公开(公告)日：2011-12-29
申请号：PCT/EP2011/060527
申请日：2011-06-22
申请人： INTRACOM S.A. TELECOM SOLUTIONS , DIMITRIOU, Athanasios , PERISSAKIS, Stylianos , PANAYIOTOPOULOS, Ilias
发明人： DIMITRIOU, Athanasios , PERISSAKIS, Stylianos , PANAYIOTOPOULOS, Ilias
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： The present invention refers to the field of wireless communications and more specifically to the design of a Parallel Multi-Pipeline Systolic Array (PMSA) architecture that implements Complex Singular Value Decomposition (CSVD) on a multi-processor device. CSVD is an important matrix factorization technique of a complex matrix P into a product of three matrices, i.e. a Hermitian unitary matrix of eigenvectors U, a diagonal matrix of eigenvalues Σ and a matrix of eigenvectors V, with several applications in Digital signal processing and wireless communications. The apparatus to perform the CSVD includes n sets of blocks, with n being a multiple of three, with each set of blocks comprising a first hardware block (60, 13), a second hardware block (70, 14) other than the first hardware block and a third hardware block (15) other than the first hardware block and the second hardware block; whereby a) the first hardware block (60, 13) of each of the n sets of blocks includes means to transform a 2x2 square matrix to a 2x2 upper triangular square matrix, b) the second hardware block (70, 14) of each of the n sets of blocks includes means to transform a 2x2 upper triangular matrix to a to a 2x2 diagonal square matrix c) the third hardware block (15) of each of the n sets of blocks includes means to swap and exchange elements of matrices. Further the apparatus includes means to transmit the output of the i-th set of blocks, with i equals 1 to n-1, to the i+1 set of blocks, and means to process a plurality of consecutive matrices simultaneously.
摘要翻译：本发明涉及无线通信领域，更具体地，涉及在多处理器设备上实现复杂奇异值分解（CSVD）的并行多管线收缩阵列（PMSA）架构的设计。 CSVD是复矩阵P成为三个矩阵的乘积的重要矩阵分解技术，即特征向量U的Hermitian酉矩阵，特征值S的对角矩阵和特征向量V的矩阵，在数字信号处理和无线通信。执行CSVD的装置包括n组块，其中n是3的倍数，每组块包括第一硬件块（60,13），除第一硬件（60,13）之外的第二硬件块（70,14）块和除第一硬件块和第二硬件块之外的第三硬件块（15）; 由此a）n组块中的每一个的第一硬件块（60,13）包括将2x2正方形矩阵变换为2x2上三角形矩形矩阵的装置，b）每个块的第二硬件块（70,14） n组块包括将2x2上三角矩阵变换为2×2对角方矩阵的装置c）n组块中的每一个的第三硬块（15）包括交换和交换矩阵元素的装置。此外，该装置包括将i个等于1到n-1的第i组块的输出传送到第i + 1个块的装置，以及同时处理多个连续矩阵的装置。

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