专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08731893B2 Circuit simulation of MOSFETs 有权
标题翻译： MOSFET的电路仿真
公开(公告)号：US08731893B2
公开(公告)日：2014-05-20
申请号：US13080154
申请日：2011-04-05
申请人： Mitiko Miura-Mattausch , Norio Sadachika , Shunta Kusu , Takaki Yoshida
发明人： Mitiko Miura-Mattausch , Norio Sadachika , Shunta Kusu , Takaki Yoshida
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.
摘要翻译：算术装置通过基于存储在存储装置中的数学表达式和装置参数进行计算来计算硅层的表面电位。同样，当硅层处于部分耗尽状态时，当硅处于完全耗尽状态时，算术装置计算掩埋氧化膜下的体层的表面电位。然后，运算装置根据计算出的硅层的表面电位，体积层的计算出的表面电位，存储在存储装置中的数学式进行计算，通过迭代计算得到体层的表面电位。算术装置根据通过迭代计算获得的体层的表面电位和存储在存储装置中的数学表达式进行计算，并计算硅层的下表面电位。

2. 发明授权

US5761082A Method for manufacturing an integrated circuit 失效
标题翻译：集成电路的制造方法
公开(公告)号：US5761082A
公开(公告)日：1998-06-02
申请号：US799493
申请日：1997-02-12
申请人： Mitiko Miura-Mattausch
发明人： Mitiko Miura-Mattausch
IPC分类号： H01L21/8234 , G06F17/50 , H01L21/82 , H01L27/088
CPC分类号： G06F17/5036
摘要： For manufacturing an integrated circuit, the production of a design for the circuit that comprises a plurality of MOS transistors is controlled by employment of a circuit simulator. ##EQU1## are calculated in the circuit simulator for the terminal nodes of the MOS transistors upon prescription of the voltages between gate and source V.sub.gs, between drain and source V.sub.ds, and between the substrate and source V.sub.bs in a consistent transistor model wherein drift, diffusion and short-channel effects are taken into consideration.
摘要翻译：为了制造集成电路，通过使用电路模拟器来控制包括多个MOS晶体管的电路的设计的生产。在用于MOS晶体管的端子节点的电路模拟器中，在栅极和源极Vgs之间，漏极和源极Vds之间以及基板和源极之间的电压模拟器中，在一致的晶体管模型中计算出，其中漂移，扩散并考虑短通道效应。

3. 发明申请

US20110184708A1 SIMULATION METHOD AND SIMULATION APPARATUS 有权
标题翻译：模拟方法和仿真设备
公开(公告)号：US20110184708A1
公开(公告)日：2011-07-28
申请号：US13080154
申请日：2011-04-05
申请人： Mitiko MIURA-MATTAUSCH , Norio Sadachika , Shunta Kusu , Takaki Yoshida
发明人： Mitiko MIURA-MATTAUSCH , Norio Sadachika , Shunta Kusu , Takaki Yoshida
IPC分类号： G06F17/50 , G06F7/60
CPC分类号： G06F17/5036
摘要： An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by, iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.
摘要翻译：算术装置通过基于存储在存储装置中的数学表达式和装置参数进行计算来计算硅层的表面电位。同样，当硅层处于部分耗尽状态时，当硅处于完全耗尽状态时，算术装置计算掩埋氧化膜下的体层的表面电位。运算装置然后根据计算出的硅层表面电位，体积层的计算出的表面电位和存储在存储装置中的数学式进行计算，并通过迭代计算得到体层的表面电位。算术装置根据通过迭代计算获得的体层的表面电位和存储在存储装置中的数学表达式进行计算，并计算硅层的下表面电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式