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1. 发明授权

US06623760B1 Method of preparing particles for agglomeration 有权
标题翻译：制备团聚颗粒的方法
公开(公告)号：US06623760B1
公开(公告)日：2003-09-23
申请号：US09490796
申请日：2000-01-26
申请人： Tsong-Toh Yang , Stephen K. C. Yu , Charles G. Eckhart , Michael B. Mitchell
发明人： Tsong-Toh Yang , Stephen K. C. Yu , Charles G. Eckhart , Michael B. Mitchell
IPC分类号： A61K914
CPC分类号： A61K9/145 , A61K31/167 , A61K31/58
摘要： Methods of preparing particulates for agglomeration, having a specified particle size distribution and desired convertible amorphous content, are described. The method involves a plurality of micronizing steps at least two of which are separated by a curing step. In the curing step, a stimulus such as humidity may be used to crystallize at least some, and in many instances preferably all, of the convertible amorphous content.
摘要翻译：描述了制备具有特定粒度分布和所需可转化非晶体含量的附聚颗粒的方法。该方法涉及多个微粉化步骤，其中至少两个通过固化步骤分离。在固化步骤中，可以使用诸如湿度的刺激来使至少一些，并且在许多情况下优选全部可结晶的无定形含量。

2. 发明授权

US06506767B1 8-chloro-6,11-dihydro-11-(4-piperidylidine)-5H-benzo[5,6]cyclohepta[1-2-b] pyridine 失效
标题翻译： 8-氯-6,11-二氢-11-（4-哌啶基）-5H-苯并[5,6]环庚并[1-2-b]吡啶
公开(公告)号：US06506767B1
公开(公告)日：2003-01-14
申请号：US09108689
申请日：1998-07-01
申请人： Doris P. Schumacher , Junning Lee , Lawrence R. Rogers , Charles G. Eckhart , Naneshwar S. Sawant , Michael B. Mitchell
发明人： Doris P. Schumacher , Junning Lee , Lawrence R. Rogers , Charles G. Eckhart , Naneshwar S. Sawant , Michael B. Mitchell
IPC分类号： C07D40108
CPC分类号： C07D401/04
摘要： Crystalline polymorphs of 8-chloro-6,11-dihydro-11-(4-piperidylidene)-5H-benzo[5,6]cycloheptic[1,2-b]pyridine represented by the formula pharmaceutical compositions containing such polymorphs, and methods of using such polymorphs to treat allergic reactions in mammals such as man are disclosed.
摘要翻译：由含有这种多晶型物的药物组合物表示的8-氯-6,11-二氢-11-（4-哌啶基）-5H-苯并[5,6]环庚并[1,2-b]吡啶的结晶多晶型物，以及公开了使用这种多晶型物来治疗哺乳动物如人的过敏反应

3. 发明授权

US08301992B2 System and apparatus for error-correcting register files 失效
标题翻译：用于纠错寄存器文件的系统和设备
公开(公告)号：US08301992B2
公开(公告)日：2012-10-30
申请号：US12537890
申请日：2009-08-07
申请人： Anthony J. Bybell , Michael B. Mitchell , Jason M. Sullivan
发明人： Anthony J. Bybell , Michael B. Mitchell , Jason M. Sullivan
IPC分类号： G06F11/00 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/1666 , G06F11/1405 , G06F11/1658 , G06F11/20
摘要： A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.
摘要翻译：一种用于使寄存器文件能够从奇偶校验错误的检测中恢复的方法，系统和计算机程序产品。第一寄存器文件和第二寄存器文件与并行文件结构相关联。当检测到奇偶校验错误时，系统确定第一寄存器文件或第二寄存器文件是否与奇偶校验错误相关联。被确定为具有奇偶校验错误的寄存器文件与违规寄存器相关联，并且非违例寄存器与良好寄存器文件相关联。在检测到奇偶校验错误之后，系统执行修复序列，由此与违规寄存器相关联的寄存器文件从与非违规寄存器相关联的寄存器文件中接收数据。错误的寄存器文件在使用或不使用奇偶校验中断的情况下从奇偶校验错误中恢复。

4. 发明申请

US20110035643A1 System and Apparatus for Error-Correcting Register Files 失效
标题翻译：用于错误校正寄存器文件的系统和设备
公开(公告)号：US20110035643A1
公开(公告)日：2011-02-10
申请号：US12537890
申请日：2009-08-07
申请人： Anthony J. Bybell , Michael B. Mitchell , Jason M. Sullivan
发明人： Anthony J. Bybell , Michael B. Mitchell , Jason M. Sullivan
IPC分类号： H03M13/00 , G06F11/16 , G06F11/08 , G06F11/00
CPC分类号： G06F11/1666 , G06F11/1405 , G06F11/1658 , G06F11/20
摘要： A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.
摘要翻译：一种用于使寄存器文件能够从奇偶校验错误的检测中恢复的方法，系统和计算机程序产品。第一注册文件和第二注册文件与并行文件结构相关联。当检测到奇偶校验错误时，系统确定第一寄存器文件或第二寄存器文件是否与奇偶校验错误相关联。被确定为具有奇偶校验错误的寄存器文件与违规寄存器相关联，并且非违例寄存器与“好”寄存器文件相关联。在检测到奇偶校验错误之后，系统执行修复序列，由此与违规寄存器相关联的寄存器文件从与非违规寄存器相关联的寄存器文件中接收数据。错误的寄存器文件在使用或不使用奇偶校验中断的情况下从奇偶校验错误中恢复。

5. 发明申请

US20090154283A1 System for Blocking Multiple Memory Read Port Activation 有权
标题翻译：用于阻止多内存读端口激活的系统
公开(公告)号：US20090154283A1
公开(公告)日：2009-06-18
申请号：US11954791
申请日：2007-12-12
申请人： Anthony Correale, JR. , Matthew W. Baker , Benjamin J. Bowers , Michael B. Mitchell , Nishith Rohatgi
发明人： Anthony Correale, JR. , Matthew W. Baker , Benjamin J. Bowers , Michael B. Mitchell , Nishith Rohatgi
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C7/1045
摘要： A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.
摘要翻译：一种用于阻止多个存储器读端口激活的系统，包括第一存储器读端口字线驱动器，其包括具有连接到第一缓冲器的输入的输出的第一极性保持锁存器，以及包括第二存储器读端口字线驱动器的第二存储器读端口字线驱动器，极性保持锁存器，其输出连接到阻塞开关的输入端，第二缓冲器的输入端连接到阻塞开关的输出，其中阻塞开关的第二输入端也连接到第一极性保持锁存器并且所述阻塞开关被配置为根据所述阻塞开关的第二输入的信号断言来允许或阻止所述阻塞开关的输入和输出之间的信号传输。

6. 发明授权

US07319578B2 Digital power monitor and adaptive self-tuning power management 有权
标题翻译：数字功率监控和自适应自整定电源管理
公开(公告)号：US07319578B2
公开(公告)日：2008-01-15
申请号：US11148090
申请日：2005-06-08
申请人： James N. Dieffenderfer , Praveen Karandikar , Michael B. Mitchell , Thomas P. Speier , Paul M. Steinmetz
发明人： James N. Dieffenderfer , Praveen Karandikar , Michael B. Mitchell , Thomas P. Speier , Paul M. Steinmetz
IPC分类号： H02H5/04
CPC分类号： G06F1/3203 , G06F1/3243 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A method and apparatus are provided for determining power events on an I/C chip for undissipated power to the chip, and wherein the chip includes a plurality of separately regulatable power consumers. A structure is provided for monitoring the occurrence of each power event to each power consumer, and determining the dissipation of power from each power event, and controlling power used by the chip responsive to the amount of undissipated power.
摘要翻译：提供了一种方法和装置，用于确定I / C芯片上对于芯片的未消耗电力的功率事件，并且其中芯片包括多个单独调节的功率消耗器。提供了一种结构，用于监测每个电力消费者的每个电力事件的发生，以及确定来自每个电力事件的功率的耗散，以及响应于未消耗电力的量来控制芯片使用的电力。

7. 发明授权

US4782159A Process for preparing beta-methyl-gamma-oxo-4-(4-oxo-1(4H)-pyridinyl) derivative of benzene butanoic acid 失效
标题翻译：苯丁酸的β-甲基-γ-氧代-4-（4-氧代-1（4H） - 吡啶基）衍生物的制备方法
公开(公告)号：US4782159A
公开(公告)日：1988-11-01
申请号：US149782
申请日：1988-01-29
申请人： Michael B. Mitchell , Kiritkant D. Pancholi
发明人： Michael B. Mitchell , Kiritkant D. Pancholi
IPC分类号： C07D213/68 , C07D211/86
CPC分类号： C07D213/68
摘要： A process for the prepartion of 3-[4-(4-oxo-1,4-dihydropyridin-1-yl)benzoyl]butanoic acid which comprises the reaction of 3-(4-fluorobenzoyl)butanoic acid with 4-hydroxypyridine under aqueous conditions in the presence of a base.
摘要翻译：制备3- [4-（4-氧代-1,4-二氢吡啶-1-基）苯甲酰基]丁酸的方法，其包括3-（4-氟苯甲酰基）丁酸与4-羟基吡啶在水溶液基地存在的条件。

8. 发明授权

US07672188B2 System for blocking multiple memory read port activation 有权
标题翻译：阻止多个内存读取端口激活的系统
公开(公告)号：US07672188B2
公开(公告)日：2010-03-02
申请号：US11954791
申请日：2007-12-12
申请人： Anthony Correale, Jr. , Matthew W. Baker , Benjamin J. Bowers , Michael B. Mitchell , Nishith Rohatgi
发明人： Anthony Correale, Jr. , Matthew W. Baker , Benjamin J. Bowers , Michael B. Mitchell , Nishith Rohatgi
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C7/1045
摘要： A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch.
摘要翻译：一种用于阻止多个存储器读端口激活的系统，包括第一存储器读端口字线驱动器，其包括具有连接到第一缓冲器的输入的输出的第一极性保持锁存器，以及包括第二存储器读端口字线驱动器的第二存储器读端口字线驱动器，极性保持锁存器，其输出连接到阻塞开关的输入端，第二缓冲器的输入端连接到阻塞开关的输出，其中阻塞开关的第二输入端也连接到第一极性保持锁存器并且所述阻塞开关被配置为根据所述阻塞开关的第二输入的信号断言来允许或阻止所述阻塞开关的输入和输出之间的信号传输。

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