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1. 发明授权

US09240410B2 Group III-N nanowire transistors 有权
公开(公告)号：US09240410B2
公开(公告)日：2016-01-19
申请号：US13976413
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L27/088 , H01L29/66 , H01L29/775 , H01L29/778 , H01L29/786 , H01L29/78 , B82Y10/00 , H01L29/06 , H01L29/20
CPC分类号： H01L29/158 , B82Y10/00 , H01L21/02603 , H01L23/66 , H01L27/0605 , H01L27/0886 , H01L29/045 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/2003 , H01L29/205 , H01L29/42392 , H01L29/66431 , H01L29/66462 , H01L29/66469 , H01L29/66522 , H01L29/66742 , H01L29/775 , H01L29/778 , H01L29/7786 , H01L29/785 , H01L29/78618 , H01L29/78681 , H01L29/78696 , H01L2223/6677 , Y10S977/938
摘要： A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

2. 发明授权

US08664694B2 Field effect transistor with narrow bandgap source and drain regions and method of fabrication 有权
公开(公告)号：US08664694B2
公开(公告)日：2014-03-04
申请号：US13752272
申请日：2013-01-28
申请人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
发明人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/267 , H01L29/41783 , H01L29/4236 , H01L29/452 , H01L29/517 , H01L29/66522 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/7836 , H01L29/785 , H01L29/78603 , H01L29/78618 , H01L29/78681
摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

3. 发明申请

US20130279145A1 GROUP III-N NANOWIRE TRANSISTORS 有权
标题翻译： III-N纳米晶体管
公开(公告)号：US20130279145A1
公开(公告)日：2013-10-24
申请号：US13976413
申请日：2011-12-19
申请人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
发明人： Han Wui Then , Robert Chau , Benjamin Chu-Kung , Gilbert Dewey , Jack Kavalieros , Matthew Metz , Niloy Mukherjee , Ravi Pillarisetty , Marko Radosavljevic
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/158 , B82Y10/00 , H01L21/02603 , H01L23/66 , H01L27/0605 , H01L27/0886 , H01L29/045 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/2003 , H01L29/205 , H01L29/42392 , H01L29/66431 , H01L29/66462 , H01L29/66469 , H01L29/66522 , H01L29/66742 , H01L29/775 , H01L29/778 , H01L29/7786 , H01L29/785 , H01L29/78618 , H01L29/78681 , H01L29/78696 , H01L2223/6677 , Y10S977/938
摘要： A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
摘要翻译： III-N族纳米线设置在基板上。纳米线的纵向长度被限定为第一组III-N材料的沟道区域，与沟道区域的第一端电耦合的源极区域和与沟道区域的第二端电耦合的漏极区域。第一组III-N材料上的第二组III-N材料用作纳米线表面上的电荷诱导层和/或阻挡层。栅极绝缘体和/或栅极导体在通道区域内的纳米线周围同轴地包裹。排水和源极接触件可以类似地同轴地围绕漏极和源极区域包裹。

4. 发明申请

US20090142897A1 FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION 有权
标题翻译：具有窄带源和漏区的场效应晶体管和制造方法
公开(公告)号：US20090142897A1
公开(公告)日：2009-06-04
申请号：US12343400
申请日：2008-12-23
申请人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
发明人： Robert S. Chau , Suman Datta , Jack Kavalieros , Justin K. Brask , Mark L. Doczy , Matthew Metz
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/267 , H01L29/41783 , H01L29/4236 , H01L29/452 , H01L29/517 , H01L29/66522 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7827 , H01L29/7836 , H01L29/785 , H01L29/78603 , H01L29/78618 , H01L29/78681
摘要： A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
摘要翻译：描述具有窄带隙半导体源极/漏极区域的晶体管。晶体管包括形成在形成于硅层上的栅介质层上的栅电极。一对源极/漏极区域形成在栅电极的相对侧上，其中所述一对源极/漏极区域包括形成在栅电极的相对侧上的硅层中的窄带隙半导体膜。

5. 发明申请

US20070126067A1 Angled implantation for removal of thin film layers 失效
标题翻译：用于去除薄膜层的角度植入
公开(公告)号：US20070126067A1
公开(公告)日：2007-06-07
申请号：US11293753
申请日：2005-12-01
申请人： Michael Hattendorf , Justin Brask , Justin Sandford , Jack Kavalieros , Matthew Metz
发明人： Michael Hattendorf , Justin Brask , Justin Sandford , Jack Kavalieros , Matthew Metz
IPC分类号： H01L21/338 , H01L29/94
CPC分类号： H01L21/28114 , H01L21/26586 , H01L21/31111 , H01L21/31155 , H01L21/32136 , H01L21/32137 , H01L29/42376 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.
摘要翻译：本发明的实施例提供一种具有反向锥形栅极电极和栅极电介质层的器件，其长度接近栅极长度。在一个实施例中，这可以通过用一个或多个成角度的离子注入来改变覆盖介电层的部分，然后去除覆盖介电层的改变的部分来完成。

6. 发明申请

US20070123003A1 Dielectric interface for group III-V semiconductor device 有权
标题翻译： III-V族半导体器件的介质界面
公开(公告)号：US20070123003A1
公开(公告)日：2007-05-31
申请号：US11292399
申请日：2005-11-30
申请人： Justin Brask , Suman Datta , Mark Doczy , James Blackwell , Matthew Metz , Jack Kavalieros , Robert Chau
发明人： Justin Brask , Suman Datta , Mark Doczy , James Blackwell , Matthew Metz , Jack Kavalieros , Robert Chau
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译：描述了III-V族半导体器件及其制造方法。高k电介质通过硫族化物区域连接到约束区域。

7. 发明申请

US20060252271A1 Atomic layer deposition using photo-enhanced bond reconfiguration 有权
标题翻译：使用光增强键重构的原子层沉积
公开(公告)号：US20060252271A1
公开(公告)日：2006-11-09
申请号：US11483295
申请日：2006-07-06
申请人： Robert Chau , Matthew Metz , Scott Hareland
发明人： Robert Chau , Matthew Metz , Scott Hareland
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： C30B29/22 , C30B25/105 , C30B25/14 , C30B29/16
摘要： An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. After the substrate or layer has reacted with the first reactant, the substrate or layer is exposed to a second reactant. During or after exposure to the second reactant, electromagnetic radiation is applied to the substrate or layer. The electromagnetic radiation excites any defective bonds that may form in the deposition process to an energy level high enough to cause the elements forming the defective bonds to react with other elements contained in the second reactant. The reaction forms desirable bonds which attach to the substrate or previous layer to form an additional new layer.
摘要翻译：当形成集成电路器件时，原子层沉积工艺可以减少在衬底或原子层上沉积原子层时形成的不良键。当形成层时，将基底或先前的层暴露于第一反应物。在衬底或层已经与第一反应物反应之后，衬底或层暴露于第二反应物。在暴露于第二反应物期间或之后，电磁辐射被施加到基底或层上。电磁辐射激发在沉积过程中可能形成的任何有缺陷的键，其能级高到足以导致形成缺陷键的元素与包含在第二反应物中的其它元素反应。该反应形成了附着到基底或先前的层以形成另外的新层的理想的键。

8. 发明申请

US20060237801A1 Compensating for induced strain in the channels of metal gate transistors 审中-公开
标题翻译：补偿金属栅晶体管通道中的诱导应变
公开(公告)号：US20060237801A1
公开(公告)日：2006-10-26
申请号：US11110485
申请日：2005-04-20
申请人： Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Suman Datta , Brian Doyle , Robert Chau
发明人： Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Suman Datta , Brian Doyle , Robert Chau
IPC分类号： H01L29/15
CPC分类号： H01L29/4966 , H01L21/823807 , H01L21/823842 , H01L29/66545 , H01L29/7843 , H01L29/7849
摘要： Strained channel field effect transistors may have a threshold voltage shift. This threshold voltage shift may be compensated for by adjusting channel doping. But this also adversely affects mobility. The threshold voltage shift may be compensated, without adversely affecting mobility, by tailoring the workfunction of a metal gate electrode used in the transistor to adequately compensate for that threshold voltage shift. For example, in some embodiments, an appropriate metal may be selected with a slightly higher workfunction or, in other cases, the workfunction of a selected metal may be adjusted by, for example, doping the metal gate electrode with a material which increases the workfunction of the gate electrode.
摘要翻译：应变通道场效应晶体管可具有阈值电压偏移。该阈值电压偏移可以通过调整沟道掺杂来补偿。但这也对行动不利。可以通过调整在晶体管中使用的金属栅电极的功函数来充分补偿该阈值电压偏移来补偿阈值电压偏移而不会不利地影响迁移率。例如，在一些实施例中，可以选择具有略高的功函数的合适的金属，或者在其他情况下，可以通过例如用增加功函数的材料掺杂金属栅电极来调整所选金属的功函数的栅电极。

9. 发明申请

US20060189156A1 Method for making a semiconductor device having a high-k gate dielectric 有权
标题翻译：制造具有高k栅极电介质的半导体器件的方法
公开(公告)号：US20060189156A1
公开(公告)日：2006-08-24
申请号：US11064648
申请日：2005-02-23
申请人： Mark Doczy , Jack Kavalieros , Justin Brask , Matthew Metz , Suman Datta , Brian Doyle , Robert Chau
发明人： Mark Doczy , Jack Kavalieros , Justin Brask , Matthew Metz , Suman Datta , Brian Doyle , Robert Chau
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02244 , H01L21/02175 , H01L21/28194 , H01L21/28229 , H01L21/31683 , H01L21/31691 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/78
摘要： A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.
摘要翻译：描述制造半导体器件的方法。该方法包括形成接触金属氧化物层的高k栅介质层。金属氧化物层通过形成金属层，然后氧化金属层而产生。

10. 发明申请

US20060121678A1 Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode 有权
标题翻译：制造具有高k栅极电介质和金属栅电极的半导体器件的方法
公开(公告)号：US20060121678A1
公开(公告)日：2006-06-08
申请号：US11006218
申请日：2004-12-07
申请人： Justin Brask , Sangwoo Pae , Jack Kavalieros , Matthew Metz , Mark Doczy , Suman Datta , Robert Chau , Jose Maiz
发明人： Justin Brask , Sangwoo Pae , Jack Kavalieros , Matthew Metz , Mark Doczy , Suman Datta , Robert Chau , Jose Maiz
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28194 , H01L21/28202 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.
摘要翻译：描述制造半导体器件的方法。该方法包括向二氧化硅层中加入氮以在基底上形成氮化二氧化硅层。在氮化二氧化硅层上形成牺牲层之后，除去牺牲层以产生沟槽。在沟槽内的氮化二氧化硅层上形成高k栅介质层，在高k栅介质层上形成金属栅电极。

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