专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2012103369A1 SINGLE LAYER BGA SUBSTRATE PROCESS 审中-公开
标题翻译：单层BGA基板工艺
公开(公告)号：WO2012103369A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/022776
申请日：2012-01-26
申请人： MARVELL WORLD TRADE LTD. , LIOU, Shiann-Ming , KAO, Huahung
发明人： LIOU, Shiann-Ming , KAO, Huahung
IPC分类号： H01L21/48 , H01L23/498
CPC分类号： H01L21/50 , H01L21/4832 , H01L21/486 , H01L23/49816 , H01L23/49861 , H01L2224/48091 , H01L2924/09701 , H01L2924/15311 , H01L2924/00014
摘要： Embodiments of the present disclosure provide semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material.
摘要翻译：本公开的实施例提供了使用金属和绝缘材料形成衬底的半导体封装技术。基板包括接合到半导体器件的第一表面和结合到印刷电路板的第二表面。使用几种最小化用于形成衬底的掩模水平的量的技术来形成衬底。例如，将金属基板图案化以在表面上形成三维图案。介电材料沉积在三维图案上。使用本文所述的几种图案化和抛光实施例，金属/电介质基板被图案化和抛光以形成结合到半导体器件的基本上平齐的表面。在一个实施例中，金属/电介质基板的顶表面被图案化以暴露下面的金属基底，金属基底的底表面被抛光以与电介质材料基本齐平。

2. 发明申请

WO2011087798A1 PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：具有半导体基板的封装组件
公开(公告)号：WO2011087798A1
公开(公告)日：2011-07-21
申请号：PCT/US2010/061630
申请日：2010-12-21
申请人： MARVELL WORLD TRADE LTD. , LIOU, Shiann-Ming , SUTARDJA, Sehat , WU, Albert , CHENG, Chuan-Cheng , WEI, Chien-Chuan
发明人： LIOU, Shiann-Ming , SUTARDJA, Sehat , WU, Albert , CHENG, Chuan-Cheng , WEI, Chien-Chuan
IPC分类号： H01L23/14 , H01L23/498 , H01L23/60 , H01L25/065
CPC分类号： H01L23/42 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/60 , H01L24/11 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12035 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种方法，其包括提供包括半导体材料的半导体衬底，在半导体衬底上形成电介质层，在电介质层上形成互连层，将半导体管芯附着到半导体衬底上，半导体管芯的有源侧到互连层，互连层以引导半导体管芯的电信号。可以描述和/或要求保护其他实施例。

3. 发明申请

WO2010129484A1 DIE EXPOSED CHIP PACKAGE 审中-公开
标题翻译： DIE曝光芯片包装
公开(公告)号：WO2010129484A1
公开(公告)日：2010-11-11
申请号：PCT/US2010/033436
申请日：2010-05-03
申请人： MARVELL WORLD TRADE LTD. , LIU, Chenglin , LIOU, Shiann-Ming
发明人： LIU, Chenglin , LIOU, Shiann-Ming
IPC分类号： H01L23/433 , H01L23/31
CPC分类号： H01L23/4334 , H01L21/565 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： This disclosure describes a chip package. In one embodiment, a semiconductor chip package includes a thermal dissipater placed on top of an integrated-circuit die, the thermal dissipater having a same or similar coefficient of thermal expansion as that of the integrated-circuit die.
摘要翻译：本公开描述了芯片封装。在一个实施例中，半导体芯片封装包括放置在集成电路管芯顶部的散热器，该散热器具有与集成电路管芯相同或相似的热膨胀系数。

4. 发明申请

WO2007089723A3 THERMAL ENHANCED PACKAGE 审中-公开
标题翻译：热增强包装
公开(公告)号：WO2007089723A3
公开(公告)日：2008-06-05
申请号：PCT/US2007002432
申请日：2007-01-29
申请人： MARVELL WORLD TRADE LTD , LIU CHENGLIN , LIOU SHIANN-MING
发明人： LIU CHENGLIN , LIOU SHIANN-MING
IPC分类号： H01L23/28
CPC分类号： H01L23/3128 , H01L23/367 , H01L23/5389 , H01L24/19 , H01L2223/6677 , H01L2224/12105 , H01L2224/73267 , H01L2224/92224 , H01L2924/01004 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01051 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/19041 , H01L2924/00
摘要： A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.
摘要翻译：一种制造集成电路封装的方法。该方法包括将半导体管芯的第一表面附接到导热和/或导电的衬底，在半导体管芯的第二表面上形成多个管芯连接器，并将半导体管芯和多个管芯连接器封装在密封剂材料。该方法还包括去除一部分密封剂材料以暴露多个模具连接器中的一个或多个，由此形成路由表面。该方法还包括在路由表面上形成多个导电迹线。多个导电迹线中的每一个的特征在于与多个管芯连接器之一电连通的第一部分和与封装连接器电连通的第二部分。

5. 发明申请

WO2014043233A1 DUAL ROW QUAD FLAT NO-LEAD SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：双向四边形平面无铅半导体封装
公开(公告)号：WO2014043233A1
公开(公告)日：2014-03-20
申请号：PCT/US2013/059262
申请日：2013-09-11
申请人： MARVELL WORLD TRADE LTD. , LIU, Chenglin , LIAO, Sheng, C. , LIOU, Shiann-Ming
发明人： LIU, Chenglin , LIAO, Sheng, C. , LIOU, Shiann-Ming
IPC分类号： H01L23/495 , H01L23/31
CPC分类号： H01L23/49548 , H01L23/3107 , H01L23/49503 , H01L23/49541 , H01L23/50 , H01L24/32 , H01L2224/29101 , H01L2924/014
摘要： Some of the embodiments of the present disclosure provide a Quad Flat No-Lead package comprising: an outer row of outer peripheral leads disposed on an outer periphery of a bottom surface of the Quad Flat No-Lead package; and an inner row of inner peripheral leads disposed on an inner periphery of the bottom surface of the Quad Flat No-Lead package, wherein each of the inner peripheral leads has a substantially rectangular shape, and wherein the substantially rectangular shape has two rounded corners adjacent to the outer row of outer peripheral leads.
摘要翻译：本公开的一些实施例提供了四平面无引线封装，其包括：设置在四边形扁平无铅封装的底表面的外周上的外排外周引线; 以及设置在四边形扁平无铅封装的底面的内周的内周引线的内排，其中每个内周引线具有大致矩形形状，并且其中大致矩形形状具有相邻的两个圆角到外周边引线的外排。

6. 发明申请

WO2011097089A2 RECESSED SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：凹陷的半导体基板
公开(公告)号：WO2011097089A2
公开(公告)日：2011-08-11
申请号：PCT/US2011/022370
申请日：2011-01-25
申请人： MARVELL WORLD TRADE LTD. , WU, Albert , CHEN, Roawen , HAN, Chung, Chyung , LIOU, Shiann-Ming , WEI, Chien-Chuan , CHANG, Runzi , WU, Scott , CHENG, Chuan-Cheng
发明人： WU, Albert , CHEN, Roawen , HAN, Chung, Chyung , LIOU, Shiann-Ming , WEI, Chien-Chuan , CHANG, Runzi , WU, Scott , CHENG, Chuan-Cheng
IPC分类号： H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供一种装置，其包括具有第一表面，与第一表面相对设置的第二表面的半导体衬底，其中第一表面的至少一部分凹陷以形成半导体衬底的凹入区域以及形成在半导体衬底的凹入区域中以提供半导体衬底的第一表面和第二表面之间的电或热通路的一个或多个通孔以及耦合到半导体衬底的管芯，管芯电耦合到在半导体衬底的凹陷区域中形成的一个或多个通孔。其他实施例可以被描述和/或要求保护。

7. 发明申请

WO2014158388A1 PACKAGE-ON-PACKAGE STRUCTURES 审中-公开
标题翻译：包装封装结构
公开(公告)号：WO2014158388A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/015810
申请日：2014-02-11
申请人： MARVELL WORLD TRADE LTD. , KAO, Huahung , LIOU, Shiann-Ming
发明人： KAO, Huahung , LIOU, Shiann-Ming
IPC分类号： H01L25/10 , H01L23/34 , H01L23/00 , H01L25/065
CPC分类号： H01L25/105 , H01L23/3128 , H01L23/3737 , H01L23/4275 , H01L23/4334 , H01L23/49816 , H01L23/49833 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/92 , H01L25/0655 , H01L2223/6677 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/13025 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16225 , H01L2224/291 , H01L2224/2919 , H01L2224/32225 , H01L2224/48227 , H01L2224/48463 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/35121 , H01L2924/37001 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide a package on package arrangement comprising a first package (804,904) including a substrate layer (116) including a top side (117a), and a bottom side (117b) that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface (117a), and a first die (118) coupled to the bottom side of the substrate layer. The arrangement also comprises a second package (802,902) including a plurality of rows of solder balls (806,906) and at least one of one or both of an active component or a passive component (810,910,920). The second package is attached, via the plurality of rows of solder balls, to the substantially flat surface of the top side of the substrate layer of the first package. The active component and/or a passive component (810,910,920) is attached to the substantially flat surface of the top side of the substrate layer of the first package.
摘要翻译：本公开的实施例提供了一种包装装置，其包括第一包装（804,904），第一包装（804,904）包括包括顶侧（117a）的底层（116）和与顶侧相对的底侧（117b），其中衬底层的顶侧限定了基本平坦的表面（117a），以及耦合到衬底层的底侧的第一管芯（118）。该装置还包括包括多排焊球（806,906）和活动部件或无源部件（810,910,920）中的一个或两个中的至少一个的第二封装（802,902）。第二包装通过多排焊球附接到第一包装的基底层的顶侧的基本上平坦的表面。有源部件和/或无源部件（810,910,920）附接到第一封装的衬底层的顶侧的基本上平坦的表面。

8. 发明申请

WO2013028435A1 PACKAGE-ON-PACKAGE STRUCTURES 审中-公开
标题翻译：包装封装结构
公开(公告)号：WO2013028435A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/050953
申请日：2012-08-15
申请人： Marvell World Trade Ltd. , KAO, Huahung , LIOU, Shiann-Ming
发明人： KAO, Huahung , LIOU, Shiann-Ming
IPC分类号： H01L25/10
CPC分类号： H01L25/50 , H01L21/56 , H01L21/76898 , H01L23/3128 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/11849 , H01L2224/13022 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/81191 , H01L2224/81801 , H01L2224/838 , H01L2224/92247 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2225/1088 , H01L2225/1094 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.
摘要翻译：本公开的实施例提供了一种包装装置，包括底部包装和第二包装。第一包装包括基底层，其包括（i）顶侧和（ii）与顶侧相对的底侧。此外，顶侧限定基本平坦的表面。第一封装还包括耦合到衬底层的底侧的管芯。第二封装包括多排焊球，并且第二封装通过多排焊球附接到基板层的基本上平坦的表面。

9. 发明申请

WO2011097089A3 RECESSED SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：残留的半导体衬底
公开(公告)号：WO2011097089A3
公开(公告)日：2011-11-17
申请号：PCT/US2011022370
申请日：2011-01-25
申请人： MARVELL WORLD TRADE LTD , WU ALBERT , CHEN ROAWEN , HAN CHUNG CHYUNG , LIOU SHIANN-MING , WEI CHIEN-CHUAN , CHANG RUNZI , WU SCOTT , CHENG CHUAN-CHENG
发明人： WU ALBERT , CHEN ROAWEN , HAN CHUNG CHYUNG , LIOU SHIANN-MING , WEI CHIEN-CHUAN , CHANG RUNZI , WU SCOTT , CHENG CHUAN-CHENG
IPC分类号： H01L21/48 , H01L23/13 , H01L23/14 , H01L23/498
CPC分类号： H01L25/04 , H01L21/486 , H01L21/565 , H01L21/76877 , H01L21/76898 , H01L23/13 , H01L23/147 , H01L23/3677 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/09 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/48 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/13024 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/81193 , H01L2224/83904 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15156 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了一种装置，包括具有第一表面的半导体衬底，与第一表面相对设置的第二表面，其中第一表面的至少一部分被凹入以形成半导体衬底的凹陷区域，以及形成在半导体衬底的凹陷区域中以在半导体衬底的第一表面和第二表面之间提供电或热路径的一个或多个通孔以及耦合到半导体衬底的管芯，该管芯电耦合到形成在半导体衬底的凹陷区域中的一个或多个通孔。可以描述和/或要求保护其他实施例。

10. 发明申请

WO2011066106A1 EMBEDDED CHIP PACKAGES 审中-公开
标题翻译：嵌入式芯片包
公开(公告)号：WO2011066106A1
公开(公告)日：2011-06-03
申请号：PCT/US2010/056251
申请日：2010-11-10
申请人： MARVELL WORLD TRADE LTD. , WU, Albert , LIOU, Shiann-ming , WU, Scott
发明人： WU, Albert , LIOU, Shiann-ming , WU, Scott
IPC分类号： H01L23/498 , H01L23/538
CPC分类号： H01L23/49833 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/5389 , H01L23/562 , H01L24/17 , H01L2224/16225 , H01L2224/16227 , H01L2924/07025 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/1579 , H01L2924/00
摘要： Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed.
摘要翻译：本公开的实施例提供了半导体封装的配置以及制造半导体封装的相关方法。制造半导体封装的方法包括将半导体管芯附接到第一衬底，将第二衬底附接到第一衬底，其中半导体管芯嵌入在第一衬底和第二衬底之间，并且形成电绝缘结构，以基本上封装半导体管芯，其中在第二衬底附接到第一衬底之后执行形成电绝缘结构。可以描述和/或要求保护附加实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式