专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130001681A1 MOS-DRIVEN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING MOS-DRIVEN SEMICONDUCTOR DEVICE 有权
标题翻译： MOS驱动半导体器件及制造MOS驱动半导体器件的方法
公开(公告)号：US20130001681A1
公开(公告)日：2013-01-03
申请号：US13634603
申请日：2010-05-27
申请人： Kin-On Sin , Chun-Wai Ng , Hitoshi Sumida , Yoshiaki Toyada , Akihiko Ohi , Hiroyuki Tanaka , Takeyoshi Nishimura
发明人： Kin-On Sin , Chun-Wai Ng , Hitoshi Sumida , Yoshiaki Toyada , Akihiko Ohi , Hiroyuki Tanaka , Takeyoshi Nishimura
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66734 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/4236 , H01L29/7813
摘要： A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
摘要翻译：在形成沟槽（7）之前，用于形成n +源极层（11）的掩模由衬底的表面上的氮化物膜形成。此时，确保衬底表面上的n +源层（11）的足够的宽度。由此，得到n +源极层（11）与源电极（15）之间的稳定的接触。在作为嵌入沟槽（7）中的栅电极（10a）的掺杂多晶硅上形成作为0.1微米以上且0.3微米以下的厚度的层间绝缘膜的CVD氧化膜（12），并且在CVD氧化膜（12）上形成未被氧化的未掺杂多晶硅（13）。由此，抑制CVD氧化膜（12）中的空隙的产生，并且通过不氧化非掺杂多晶硅（13），容易制造半导体装置。

2. 发明授权

US5982004A Polysilicon devices and a method for fabrication thereof 失效
标题翻译：多晶硅器件及其制造方法
公开(公告)号：US5982004A
公开(公告)日：1999-11-09
申请号：US879886
申请日：1997-06-20
申请人： Johnny Kin On Sin , Anish Kumar Kottarath Parambil
发明人： Johnny Kin On Sin , Anish Kumar Kottarath Parambil
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/225 , H01L21/336 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/788 , H01L27/01
CPC分类号： H01L29/6675 , H01L27/12 , H01L29/66825 , H01L29/78645 , H01L29/78648 , H01L29/7881
摘要： The present invention provides a novel thin film transistor device having the advantages of both conventional thin and thick film devices. The channel region of the device is elevated with respect to the source and drain regions by being made as a thin film while the source and drain regions are relatively thick. Such an arrangement provides high drive current characteristics of a thin film device, whilst mitigating the disadvantageous kink effect in the IV curve and the off-state leakage current known in conventional thin film devices. The invention also provides a fabrication method, and this method may also be employed to manufacture other novel semiconductor devices including EEPROM devices, large double layer storage capacitors and a novel conductivity modulated thin film transistor.
摘要翻译：本发明提供了一种具有传统薄膜和厚膜器件的优点的新型薄膜晶体管器件。器件的沟道区域相对于源极和漏极区域被提供为薄膜，而源极和漏极区域相对较厚。这种布置提供薄膜器件的高驱动电流特性，同时减轻IV曲线中的不利扭结效应和传统薄膜器件中已知的截止状态漏电流。本发明还提供了一种制造方法，并且该方法也可用于制造包括EEPROM器件，大双层存储电容器和新型导电性调制薄膜晶体管的其它新型半导体器件。

3. 发明授权

US10593767B2 Field plate structure for power semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10593767B2
公开(公告)日：2020-03-17
申请号：US14771095
申请日：2014-11-26
申请人： Chun Wai Ng , Iftikhar Ahmed , Johnny Kin On Sin
发明人： Chun Wai Ng , Iftikhar Ahmed , Johnny Kin On Sin
IPC分类号： H01L29/40 , H01L29/78 , H01L29/739 , H01L29/06 , H01L29/732 , H01L29/45 , H01L29/66 , H01L29/861 , H01L21/285 , H01L29/73 , H01L29/74 , H01L29/10
摘要： A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates (32, 33, 34) located between metal electrodes (21, 22, 23) at the surface of the power semiconductor device is provided. The thin semi-insulating field plates (32, 33, 34) are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.

4. 发明授权

US09825149B2 Split gate power semiconductor field effect transistor 有权
公开(公告)号：US09825149B2
公开(公告)日：2017-11-21
申请号：US15188694
申请日：2016-06-21
申请人： Jiajin Liang , Chun Wai Ng , Johnny Kin On Sin
发明人： Jiajin Liang , Chun Wai Ng , Johnny Kin On Sin
IPC分类号： H01L29/423 , H01L29/66 , H01L29/10 , H01L29/40 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/402 , H01L29/405 , H01L29/4232 , H01L29/42376 , H01L29/4238 , H01L29/66333 , H01L29/7395 , H01L29/7802
摘要： The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.

5. 发明授权

US09397178B2 Split gate power semiconductor field effect transistor 有权
标题翻译：分流栅功率半导体场效应晶体管
公开(公告)号：US09397178B2
公开(公告)日：2016-07-19
申请号：US14766594
申请日：2014-12-04
申请人： Jiajin Liang , Chun Wai Ng , Johnny Kin On Sin
发明人： Jiajin Liang , Chun Wai Ng , Johnny Kin On Sin
IPC分类号： H01L29/423 , H01L29/40 , H01L29/66 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/402 , H01L29/405 , H01L29/4232 , H01L29/42376 , H01L29/4238 , H01L29/66333 , H01L29/7395 , H01L29/7802
摘要： The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.
摘要翻译：本发明一般涉及功率场效应晶体管（FET）的结构和制造。本发明提供一种平面功率金属氧化物半导体场效应晶体管（MOSFET）结构和包括分离栅极和半绝缘场板的绝缘栅双极晶体管（IGBT）结构。本发明还提供了结构的制造方法。

6. 发明申请

US20160013279A1 FIELD PLATE STRUCTURE FOR POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：功率半导体器件的现场板结构及其制造方法
公开(公告)号：US20160013279A1
公开(公告)日：2016-01-14
申请号：US14771095
申请日：2014-11-26
申请人： Chun Wai NG , Iftikhar AHMED , Johnny Kin On SIN
发明人： Chun Wai NG , Iftikhar AHMED , Johnny Kin On SIN
IPC分类号： H01L29/40 , H01L21/285 , H01L29/73 , H01L29/74 , H01L29/78 , H01L29/739
CPC分类号： H01L29/405 , H01L21/28525 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L29/0619 , H01L29/1095 , H01L29/404 , H01L29/456 , H01L29/66136 , H01L29/73 , H01L29/732 , H01L29/7393 , H01L29/7395 , H01L29/74 , H01L29/7811 , H01L29/7816 , H01L29/7823 , H01L29/7827 , H01L29/8611
摘要： A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates (32, 33, 34) located between metal electrodes (21, 22, 23) at the surface of the power semiconductor device is provided. The thin semi-insulating field plates (32, 33, 34) are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.
摘要翻译：提供了功率半导体器件的结构和制造方法。提供位于功率半导体器件表面的金属电极（21,22,23）之间的薄半绝缘场板（32,33,34）的结构。薄的半绝缘场板（32,33,34）通过在金属化之前沉积并在金属化之后退火而形成。本发明可用于横向功率半导体器件和垂直功率半导体器件。

7. 发明申请

US20120249282A1 LARGE INDUCTANCE INTEGRATED MAGNETIC INDUCTION DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：大电感一体化磁感应装置及其制造方法
公开(公告)号：US20120249282A1
公开(公告)日：2012-10-04
申请号：US13434848
申请日：2012-03-29
申请人： Johnny Kin On Sin , Rongxiang Wu , Xiangming Fang
发明人： Johnny Kin On Sin , Rongxiang Wu , Xiangming Fang
IPC分类号： H01F5/00 , H01F41/06
CPC分类号： H01L28/10 , H01F17/0033 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus described herein are associated with integrated magnetic induction devices. A magnetic induction device can include a groove formed in a substrate, a magnetic core included in the groove and surrounded by a conductive winding that is adjacent to portion(s) of the substrate, and respective insulation layers included between the substrate and the conductive winding and between the magnetic core and the conductive winding. An inductor can further include conductive vias formed in the substrate and connected to respective portions of the conductive winding. Further, a transformer can include a groove formed in a substrate, a closed-loop/gapped magnetic core included in the groove and surrounded by first and second conductive windings that are adjacent to respective portions of the substrate, and respective insulation layers formed between the substrate and the first and second conductive windings, and between the closed-loop/gapped magnetic core and the first and second conductive windings.
摘要翻译：本文描述的方法和装置与集成磁感应装置相关联。磁感应装置可以包括形成在基板中的凹槽，包括在凹槽中并被与基板的一部分相邻的导电绕组包围的磁芯以及包括在基板和导电绕组之间的各个绝缘层并且在磁芯和导电绕组之间。电感器还可以包括形成在衬底中并连接到导电绕组的相应部分的导电通孔。此外，变压器可以包括形成在基板中的凹槽，包括在凹槽中的闭环/间隙磁芯，并且被与基板的相应部分相邻的第一和第二导电绕组围绕，并且在衬底以及第一和第二导电绕组之间，以及闭环/间隙磁芯与第一和第二导电绕组之间。

8. 发明授权

US06992352B2 Trenched DMOS devices and methods and processes for making same 失效
标题翻译：热门的DMOS设备及其制作方法和过程
公开(公告)号：US06992352B2
公开(公告)日：2006-01-31
申请号：US10441018
申请日：2003-05-20
申请人： Tommy Mau Lam Lai , Johnny Kin On Sin
发明人： Tommy Mau Lam Lai , Johnny Kin On Sin
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/7802
摘要： This invention describes a process for making a high density trench DMOS (Double-diffused Metal Oxide Semiconductor) transistor with improved gate oxide breakdown at the three-dimensional trench corners and better body contact which can improve the latch-up immunity and increase the drive current. A guard-ring mask is used to define a deep body to cover the three-dimensional trench corners, which can prevent early gate-oxide breakdown during the off-state operation. Another function of the guard-ring mask is to define self-aligned deeper trenches at the terminations of the trenches. The deeper trenches at the terminations of the trenches will result in thicker gate oxide grown at the terminations. This layer of thicker oxide is used to prevent the pre-mature gate oxide breakdown at the three-dimensional trench corners. A trench spacer is formed after the N-body drive-in step by depositing a layer of oxide and then followed by an oxide etch-back step. This spacer is used to prevent any unwanted impurities to penetrate through the trench sidewall and get into the device channel during the high dosage source implantation step.
摘要翻译：本发明描述了一种用于制造高密度沟槽DMOS（双扩散金属氧化物半导体）晶体管的方法，其具有改善的三维沟槽角上的栅极氧化物击穿和更好的机体接触，这可以提高闩锁抗扰度并增加驱动电流。保护环掩模用于定义深体以覆盖三维沟槽角，这可以防止在关闭状态操作期间的早期栅极氧化物击穿。保护环掩模的另一个功能是在沟槽的终端处限定自对准较深的沟槽。在沟槽终端处的较深的沟槽将导致在终端处生长的栅极氧化物更厚。该层较厚的氧化物用于防止三维沟槽角处的成熟前的栅极氧化物击穿。在N体驱动步骤之后通过沉积氧化物层然后再进行氧化物回蚀步骤形成沟槽间隔物。该间隔物用于防止任何不需要的杂质穿过沟槽侧壁并在高剂量源植入步骤期间进入器件通道。

9. 发明授权

US08981460B2 Power semiconductor field effect transistor structure with charge trapping material in the gate dielectric 有权
标题翻译：功率半导体场效应晶体管结构，在栅极电介质中具有电荷捕获材料
公开(公告)号：US08981460B2
公开(公告)日：2015-03-17
申请号：US13883753
申请日：2011-12-20
申请人： Johnny Kin On Sin , Xianda Zhou
发明人： Johnny Kin On Sin , Xianda Zhou
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L29/408 , H01L29/513 , H01L29/518 , H01L29/66333 , H01L29/66712 , H01L29/66833 , H01L29/7395 , H01L29/7802 , H01L29/792
摘要： The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with improved ruggedness and. In an aspect, the power semiconductor devices are power field effect transistors (FETs) having enhanced suppression of the activation of the parasitic bipolar junction transistor (BJT) and a normal threshold value. The devices comprise a doped source (14) of a first conductivity type, a doped body (15) of a second conductivity type, a source electrode (20) short-connecting the doped body and the doped source, a doped drift region (10) of the first conductivity type, a first layer (30) of a gate dielectric region (36) covering the surface of the doped drift region (10), and forming channel from the doped source (14) to the doped drift region (10), a second layer (31) of the gate dielectric region (36) over the first layer (30), a third layer (32) of the gate dielectric region (36) over the second layer (31), and a gate electrode (21) over the third layer (32).
摘要翻译：本发明公开了功率半导体器件及其制造方法，具有改进的耐用性和。一方面，功率半导体器件是具有增强的对寄生双极结型晶体管（BJT）的激活抑制和正常阈值的功率场效应晶体管（FET）。这些器件包括第一导电类型的掺杂源极（14），第二导电类型的掺杂体（15），短路连接掺杂体的源极（20）和掺杂源，掺杂漂移区（10）），覆盖掺杂漂移区（10）的表面的栅介质区（36）的第一层（30），以及从掺杂源（14）到掺杂漂移区（10）的沟道），位于第一层（30）上方的栅极电介质区域（36）的第二层（31），位于第二层（31）上方的栅极电介质区域（36）的第三层（32）（21）在第三层（32）之上。

10. 发明授权

US08754737B2 Large inductance integrated magnetic induction devices and methods of fabricating the same 有权
标题翻译：大电感集成磁感应装置及其制造方法
公开(公告)号：US08754737B2
公开(公告)日：2014-06-17
申请号：US13434848
申请日：2012-03-29
申请人： Johnny Kin On Sin , Rongxiang Wu , Xiangming Fang
发明人： Johnny Kin On Sin , Rongxiang Wu , Xiangming Fang
IPC分类号： H01F5/00 , H01F27/28 , H01L23/522 , H01F17/00 , H01L49/02
CPC分类号： H01L28/10 , H01F17/0033 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus described herein are associated with integrated magnetic induction devices. A magnetic induction device can include a groove formed in a substrate, a magnetic core included in the groove and surrounded by a conductive winding that is adjacent to portion(s) of the substrate, and respective insulation layers included between the substrate and the conductive winding and between the magnetic core and the conductive winding. An inductor can further include conductive vias formed in the substrate and connected to respective portions of the conductive winding. Further, a transformer can include a groove formed in a substrate, a closed-loop/gapped magnetic core included in the groove and surrounded by first and second conductive windings that are adjacent to respective portions of the substrate, and respective insulation layers formed between the substrate and the first and second conductive windings, and between the closed-loop/gapped magnetic core and the first and second conductive windings.
摘要翻译：本文所述的方法和装置与集成磁感应装置相关联。磁感应装置可以包括形成在基板中的凹槽，包括在凹槽中并被与基板的一部分相邻的导电绕组包围的磁芯以及包括在基板和导电绕组之间的各个绝缘层并且在磁芯和导电绕组之间。电感器还可以包括形成在衬底中并连接到导电绕组的相应部分的导电通孔。此外，变压器可以包括形成在基板中的凹槽，包括在凹槽中的闭环/间隙磁芯，并且被与基板的相应部分相邻的第一和第二导电绕组围绕，并且在基板以及第一和第二导电绕组之间以及闭环/带隙磁芯与第一和第二导电绕组之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式