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1. 发明授权

US08461812B2 Shunt regulator having over-voltage protection circuit and semiconductor device including the same 有权
标题翻译：具有过电压保护电路的分路稳压器和包括其的半导体器件
公开(公告)号：US08461812B2
公开(公告)日：2013-06-11
申请号：US12327458
申请日：2008-12-03
申请人： Han-Su Kim , Joo-Hyun Jeong
发明人： Han-Su Kim , Joo-Hyun Jeong
IPC分类号： G05F1/613
CPC分类号： G05F1/613
摘要： A shunt regulator includes a control circuit, a bypass circuit and a protection circuit. The control circuit is coupled between a first node and a ground, and generates a gate control signal in response to a voltage of the first node and a reference voltage. The bypass circuit forms a first current path between the first node and the ground in response to the gate control signal. The protection circuit has an MOS transistor that is fully turned on in response to a current flowing through the bypass circuit, and forms a second current path between the first node and the ground. Therefore, the shunt regulator occupies a relatively small area in an integrated circuit.
摘要翻译：并联调节器包括控制电路，旁路电路和保护电路。控制电路耦合在第一节点和地之间，并且响应于第一节点的电压和参考电压而产生门控制信号。旁路电路响应于门控制信号在第一节点和地之间形成第一电流路径。保护电路具有响应于流过旁路电路的电流而完全导通的MOS晶体管，并且在第一节点和地之间形成第二电流路径。因此，分流调节器在集成电路中占据相对较小的面积。

2. 发明授权

US08216860B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08216860B2
公开(公告)日：2012-07-10
申请号：US13083309
申请日：2011-04-08
申请人： Joo-hyun Jeong , Chul-ho Chung
发明人： Joo-hyun Jeong , Chul-ho Chung
IPC分类号： H01L21/02
CPC分类号： H01L21/76841 , H01L21/2855 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.
摘要翻译：一种半导体器件和制造半导体器件的方法，包括在半导体衬底上形成层间绝缘膜; 通过使用包含Fe，Co，Ni或其合金中的至少一种的靶通过溅射，在层间绝缘膜上沉积第一软磁性薄膜，靶还含有Ti，Hf或B中的至少一种，溅射为使用N2反应气体进行; 在第一软磁薄膜上形成金属膜; 通过溅射使用含有Fe，Co，Ni或其合金中的至少一种的相同或另一靶的溅射在金属膜上沉积第二软磁薄膜，靶还含有Ti，Hf或B中的至少一种，使用N 2反应气体进行溅射; 并图案化以形成电感器。

3. 发明授权

US07923814B2 Semiconductor device including an inductor having soft magnetic thin film patterns and a fabricating method of the same 有权
标题翻译：包括具有软磁薄膜图案的电感器的半导体器件及其制造方法
公开(公告)号：US07923814B2
公开(公告)日：2011-04-12
申请号：US11656451
申请日：2007-01-23
申请人： Joo-hyun Jeong , Chul-ho Chung
发明人： Joo-hyun Jeong , Chul-ho Chung
IPC分类号： H01L29/00 , H01F27/28
CPC分类号： H01L21/76841 , H01L21/2855 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an interlayer insulating film and an inductor. The inductor includes a first soft magnetic thin film pattern formed on the interlayer insulating film, the first soft magnetic film comprising a) at least one material selected from Fe, Co, Ni, or alloys thereof b) at least one element selected from Ti, Hf, or B, and c) N, a metal film pattern formed on the first soft magnetic thin film pattern and a second soft magnetic thin film pattern formed on the metal film pattern, the second soft magnetic thin film pattern comprising a) at least one material selected from Fe, Co, Ni, or alloys thereof; b) at least one element selected from Ti, Hf, or B; and c) N. Edges of the first soft magnetic thin film pattern, edges of the metal film pattern and edges of the second soft magnetic thin film pattern are vertically aligned.
摘要翻译：半导体器件包括层间绝缘膜和电感器。电感器包括形成在层间绝缘膜上的第一软磁薄膜图案，第一软磁膜包括a）至少一种选自Fe，Co，Ni的材料或其合金b）至少一种选自Ti， Hf或B，以及c）N，形成在所述第一软磁薄膜图案上的金属膜图案和形成在所述金属膜图案上的第二软磁薄膜图案，所述第二软磁薄膜图案至少包括：a）至少一种选自Fe，Co，Ni的材料或其合金; b）选自Ti，Hf或B中的至少一种元素; c）N.第一软磁薄膜图案的边缘，金属膜图案的边缘和第二软磁薄膜图案的边缘垂直对准。

4. 发明申请

US20070216510A1 Inductor and method of forming the same 有权
公开(公告)号：US20070216510A1
公开(公告)日：2007-09-20
申请号：US11804320
申请日：2007-05-17
申请人： Joo-Hyun Jeong , Chul-Ho Chung
发明人： Joo-Hyun Jeong , Chul-Ho Chung
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/34 , H01F41/041 , H01F2017/0046 , H01F2017/0073 , H01L2924/0002 , H01L2924/00
摘要： An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.

5. 发明授权

US07236081B2 Inductor and method of forming the same 有权
标题翻译：电感和形成方法
公开(公告)号：US07236081B2
公开(公告)日：2007-06-26
申请号：US11322753
申请日：2005-12-30
申请人： Joo-Hyun Jeong , Chul-Ho Chung
发明人： Joo-Hyun Jeong , Chul-Ho Chung
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/34 , H01F41/041 , H01F2017/0046 , H01F2017/0073 , H01L2924/0002 , H01L2924/00
摘要： An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.
摘要翻译：在基板上形成电感图形。在电感图案上形成具有凹凸结构的导电图案，以增加电感图案的表面积。在电感器图案上形成绝缘层。在形成凹槽之后，去除绝缘层以露出电感器图案，导电图案保形地形成在凹槽和绝缘层上。因此，电感器图案的表面积以及电感器的厚度增加以获得高品质因数的电感器。

6. 发明授权

US08962435B2 Method of forming semiconductor device having embedded strain-inducing pattern 有权
标题翻译：形成具有嵌入应变诱导图案的半导体器件的方法
公开(公告)号：US08962435B2
公开(公告)日：2015-02-24
申请号：US14508250
申请日：2014-10-07
申请人： Shigenobu Maeda , Hidenobu Fukutome , Young-Gun Ko , Joo-Hyun Jeong
发明人： Shigenobu Maeda , Hidenobu Fukutome , Young-Gun Ko , Joo-Hyun Jeong
IPC分类号： H01L21/336 , H01L29/66 , H01L21/02
CPC分类号： H01L29/7842 , H01L21/02532 , H01L21/02587 , H01L21/02636 , H01L21/02658 , H01L29/045 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
摘要翻译：半导体器件可以包括有源区，其具有提供相对的源极和漏极区之间的沟道区的鳍部。栅电极可以跨越在相对的源极和漏极区域之间的沟道区域上，并且第一和第二应变诱导结构可以在栅电极的相对侧上，并且可以被配置为在沟道区域上引起应变，其中第一和第二应变诱导结构，其包括具有一对{111}晶体取向小面的相应的相对侧。

7. 发明授权

US07405643B2 Inductor and method of forming the same 有权
标题翻译：电感和形成方法
公开(公告)号：US07405643B2
公开(公告)日：2008-07-29
申请号：US11804320
申请日：2007-05-17
申请人： Joo-Hyun Jeong , Chul-Ho Chung
发明人： Joo-Hyun Jeong , Chul-Ho Chung
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F27/34 , H01F41/041 , H01F2017/0046 , H01F2017/0073 , H01L2924/0002 , H01L2924/00
摘要： An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.
摘要翻译：在基板上形成电感图形。在电感图案上形成具有凹凸结构的导电图案，以增加电感图案的表面积。在电感器图案上形成绝缘层。在形成凹槽之后，去除绝缘层以露出电感器图案，导电图案保形地形成在凹槽和绝缘层上。因此，电感器图案的表面积以及电感器的厚度增加以获得高品质因数的电感器。

8. 发明申请

US20060158302A1 Inductor and method of forming the same 有权
标题翻译：电感和形成方法
公开(公告)号：US20060158302A1
公开(公告)日：2006-07-20
申请号：US11322753
申请日：2005-12-30
申请人： Joo-Hyun Jeong , Chul-Ho Chung
发明人： Joo-Hyun Jeong , Chul-Ho Chung
IPC分类号： H01F27/28
CPC分类号： H01F17/0006 , H01F27/34 , H01F41/041 , H01F2017/0046 , H01F2017/0073 , H01L2924/0002 , H01L2924/00
摘要： An inductor pattern is formed on a substrate. A conductive pattern having a concave-convex structure is formed on the inductor pattern to increase a surface area of the inductor pattern. An insulation layer is formed on the inductor pattern. After a groove is formed such that the insulation layer is removed to expose the inductor pattern, a conductive pattern is conformally formed on the groove and the insulation layer. Thus, a surface area of the inductor pattern as well as a thickness of an inductor increases to obtain an inductor of a high quality factor.
摘要翻译：在基板上形成电感图形。在电感图案上形成具有凹凸结构的导电图案，以增加电感图案的表面积。在电感器图案上形成绝缘层。在形成凹槽之后，去除绝缘层以露出电感器图案，导电图案保形地形成在凹槽和绝缘层上。因此，电感器图案的表面积以及电感器的厚度增加以获得高品质因数的电感器。

9. 发明申请

US20150024565A1 METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN 有权
标题翻译：形成具有嵌入式应变诱导图案的半导体器件的方法
公开(公告)号：US20150024565A1
公开(公告)日：2015-01-22
申请号：US14508250
申请日：2014-10-07
申请人： Shigenobu Maeda , Hidenobu Fukutome , Young-Gun Ko , Joo-Hyun Jeong
发明人： Shigenobu Maeda , Hidenobu Fukutome , Young-Gun Ko , Joo-Hyun Jeong
IPC分类号： H01L29/66 , H01L21/02
CPC分类号： H01L29/7842 , H01L21/02532 , H01L21/02587 , H01L21/02636 , H01L21/02658 , H01L29/045 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
摘要翻译：半导体器件可以包括有源区，其具有提供相对的源极和漏极区之间的沟道区的鳍部。栅电极可以跨越在相对的源极和漏极区域之间的沟道区域上，并且第一和第二应变诱导结构可以在栅电极的相对侧上，并且可以被配置为在沟道区域上引起应变，其中第一和第二应变诱导结构，其包括具有一对{111}晶体取向小面的相应的相对侧。

10. 发明申请

US20130341631A1 SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME 有权
标题翻译：具有嵌入式应变诱导图案的半导体器件及其形成方法
公开(公告)号：US20130341631A1
公开(公告)日：2013-12-26
申请号：US13826633
申请日：2013-03-14
申请人： Shigenobu Maeda , Hidenobu Fukutome , Young-Gun Ko , Joo-Hyun Jeong
发明人： Shigenobu Maeda , Hidenobu Fukutome , Young-Gun Ko , Joo-Hyun Jeong
IPC分类号： H01L29/04
CPC分类号： H01L29/7842 , H01L21/02532 , H01L21/02587 , H01L21/02636 , H01L21/02658 , H01L29/045 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A semiconductor device can include an active region having a fin portion providing a channel region between opposing source and drain regions. A gate electrode can cross over the channel region between the opposing source and drain regions and first and second strain inducing structures can be on opposing sides of the gate electrode and can be configured to induce strain on the channel region, where each of the first and second strain inducing structures including a respective facing side having a pair of {111} crystallographically oriented facets.
摘要翻译：半导体器件可以包括有源区，其具有提供相对的源极和漏极区之间的沟道区的鳍部。栅电极可以跨越在相对的源极和漏极区域之间的沟道区域上，并且第一和第二应变诱导结构可以在栅电极的相对侧上，并且可以被配置为在沟道区域上引起应变，其中第一和第二应变诱导结构，其包括具有一对{111}晶体取向小面的相应的相对侧。

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