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    • 5. 发明申请
    • BATTERY PACK
    • 电池组
    • US20120121937A1
    • 2012-05-17
    • US13078213
    • 2011-04-01
    • Eun-Ok KwakJeong-Deok ByunKyung-Won SeoJin-Hong An
    • Eun-Ok KwakJeong-Deok ByunKyung-Won SeoJin-Hong An
    • H01M10/42
    • H01M10/42H01M2/34
    • A battery pack is constructed with a plurality of bare cells having first and second electrodes, a protection circuit module having at least one through-holes, a first electrode lead electrically connecting the first electrodes and a second electrode lead electrically connecting the second electrodes, and a holder case having supports that support the bare cells. One end of each first and second electrode leads passes through the through-hole of the protection circuit module. The first and second electrode leads electrically connect the bare cells and balance the bare cells by transmitting at least one of voltage and current of the bare cells to the protection circuit module.
    • 电池组由具有第一和第二电极的多个裸电池构成,具有至少一个通孔的保护电路模块,电连接第一电极的第一电极引线和电连接第二电极的第二电极引线,以及 具有支撑裸电池的支架的支架壳体。 每个第一和第二电极引线的一端通过保护电路模块的通孔。 第一和第二电极引线通过将裸电池的电压和电流中的至少一个传输到保护电路模块来电连接裸电池并平衡裸电池。
    • 9. 发明授权
    • Semiconductor memory device with ferroelectric device
    • 具有铁电元件的半导体存储器件
    • US07668031B2
    • 2010-02-23
    • US11967531
    • 2007-12-31
    • Hee Bok KangJin Hong AnSuk Kyoung Hong
    • Hee Bok KangJin Hong AnSuk Kyoung Hong
    • G11C7/02
    • G11C7/14G11C11/22
    • A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device includes a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.
    • 半导体存储器件包括连接在一对位线之间并由字线控制的单晶体管(1-T)场效应晶体管(FET)型存储单元,其中不同的沟道电阻被引导到通道区域依赖 在铁电层的极性状态。 该装置包括排列成行方向的多个字线,沿列方向配置的多个位线,沿列方向排列的一对钳位虚拟线,沿列方向排列的一对基准虚拟线, 包括存储单元并形成在字线和位线交叉的区域中的单元阵列,包括存储单元的虚拟单元阵列,并形成在字线,一对声线虚拟线和一对参考虚线之间 以及连接到位线并被配置为接收钳位电压和参考电压的读出放大器和写入驱动单元。
    • 10. 发明授权
    • Phase change memory device
    • 相变存储器件
    • US07663910B2
    • 2010-02-16
    • US12135241
    • 2008-06-09
    • Hee Bok KangJin Hong AnSuk Kyoung Hong
    • Hee Bok KangJin Hong AnSuk Kyoung Hong
    • G11C11/00
    • G11C13/0038G11C13/0004G11C13/0026G11C13/004G11C2013/0054G11C2213/72
    • A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage.
    • 相变存储器件包括沿行方向布置的多个字线和沿列方向布置的多个位线。 多个基准位线和多个钳位位线在列方向上排列。 布置包括相变电阻单元的单元阵列块,其中字线和位线相交。 形成参考单元阵列块,其中字线和参考位线相交。 参考单元阵列块被配置为输出参考电流。 形成钳位单元阵列块,其中字线和钳位位线相交。 钳位单元阵列块被配置为输出钳位电流。 感测放大器连接到每个位线,并且被配置为接收钳位电压和参考电压。