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1. 发明授权

US07291531B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US07291531B2
公开(公告)日：2007-11-06
申请号：US11048995
申请日：2005-02-02
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

2. 发明申请

US20050130371A1 Method of fabricating semiconductor device having capacitor 有权
公开(公告)号：US20050130371A1
公开(公告)日：2005-06-16
申请号：US11048995
申请日：2005-02-02
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/3213
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

3. 发明授权

US06867096B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US06867096B2
公开(公告)日：2005-03-15
申请号：US10855165
申请日：2004-05-27
申请人： Sung-IL Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-IL Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/3213
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

4. 发明授权

US06319824B1 Method of forming a contact hole in a semiconductor device 有权
标题翻译：在半导体器件中形成接触孔的方法
公开(公告)号：US06319824B1
公开(公告)日：2001-11-20
申请号：US09453215
申请日：1999-12-03
申请人： Se-hyeong Lee , Ji-chul Shin
发明人： Se-hyeong Lee , Ji-chul Shin
IPC分类号： H01L214763
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76804 , H01L27/10855
摘要： A method of forming a contact hole for a semiconductor device, and a method of forming a capacitor for a semiconductor device using the same. An interlayer dielectric layer, a contact mask material layer including of a material having a high etching selectivity with respect to the interlayer dielectric layer, an anti-reflection layer, and a photoresist layer, are formed on a semiconductor substrate. A photoresist pattern is formed from the photoresist layer to expose part of the anti-reflection layer, and a flow process is performed on the photoresist pattern to expose even a smaller amount of the anti-reflection layer. The anti-reflection layer and the contact mask material layer are then etched to expose part of the interlayer dielectric layer, and the interlayer dielectric layer is etched to form a contact hole.
摘要翻译：一种形成用于半导体器件的接触孔的方法，以及形成使用其的半导体器件的电容器的方法。在半导体衬底上形成层间介质层，包括相对于层间电介质层具有高蚀刻选择性的材料的接触掩模材料层，抗反射层和光致抗蚀剂层。由光致抗蚀剂层形成光致抗蚀剂图案以暴露部分防反射层，并且在光致抗蚀剂图案上进行流程处理以暴露甚至更少量的抗反射层。然后对抗反射层和接触掩模材料层进行蚀刻以暴露部分层间电介质层，并蚀刻层间电介质层以形成接触孔。

5. 发明授权

US6013549A DRAM cell capacitor and method for manufacturing the same 有权
标题翻译： DRAM单元电容器及其制造方法
公开(公告)号：US6013549A
公开(公告)日：2000-01-11
申请号：US148633
申请日：1998-09-04
申请人： Min-Seog Han , Ji-Chul Shin , Seok Woo Nam , Hyung-Seok Lee
发明人： Min-Seog Han , Ji-Chul Shin , Seok Woo Nam , Hyung-Seok Lee
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L28/84
摘要： A DRAM cell capacitor is provided wherein a capacitor bottom electrode has an HSG (Hemi-Spherical Grain) layer formed thereon so as to increase capacitance of the capacitor. In the DRAM cell capacitor, the capacitor bottom electrode has an angled shape at a top edge thereof, and the HSG silicon layer is not formed on the top edge of the capacitor bottom electrode. A method for manufacturing the DRAM cell capacitor comprises etching an upper portion of the conductive layer using the photoresist pattern as a mask, and at the same time forming a polymer on both sidewalls of the photoresist pattern to etch the upper portion thereof and thereby to make a top edge of the conductive layer be angled. The method further comprises etching a remaining portion of the conductive layer sing a combination of the photoresist pattern and the polymer as a mask until an upper surface of the interlayer insulating layer is exposed, to thereby form the capacitor bottom electrode.
摘要翻译：提供一种DRAM单元电容器，其中电容器底部电极具有形成在其上的HSG（半球形晶粒）层，以增加电容器的电容。在DRAM单元电容器中，电容器底部电极在其顶部边缘处具有成角度的形状，并且HSG硅层不形成在电容器底部电极的顶部边缘上。用于制造DRAM单元电容器的方法包括使用光致抗蚀剂图案作为掩模蚀刻导电层的上部，并且同时在光致抗蚀剂图案的两个侧壁上形成聚合物以蚀刻其上部，从而使导电层的顶部边缘成角度。该方法还包括蚀刻导电层的剩余部分，将光致抗蚀剂图案和聚合物的组合作为掩模进行刻蚀，直到层间绝缘层的上表面露出，从而形成电容器底部电极。

6. 发明申请

US20080087931A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CAPACITOR 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US20080087931A1
公开(公告)日：2008-04-17
申请号：US11869400
申请日：2007-10-09
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L27/108 , H01L21/3205 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

7. 发明授权

US08941165B2 Methods of fabricating integrated circuit capacitors having u-shaped lower capacitor electrodes 有权
标题翻译：制造具有u形下电容器电极的集成电路电容器的方法
公开(公告)号：US08941165B2
公开(公告)日：2015-01-27
申请号：US12779300
申请日：2010-05-13
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L27/108 , H01L49/02 , H01L21/3213 , H01L21/314 , H01L21/316
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

8. 发明授权

US06215143B1 DRAM cell capacitor having hemispherical grain silicon on a selected portion of a storage node 有权
标题翻译： DRAM单元电容器在存储节点的选定部分上具有半球形晶体硅
公开(公告)号：US06215143B1
公开(公告)日：2001-04-10
申请号：US09377156
申请日：1999-08-19
申请人： Min-Seog Han , Ji-Chul Shin , Seok Woo Nam , Hyung-Seok Lee
发明人： Min-Seog Han , Ji-Chul Shin , Seok Woo Nam , Hyung-Seok Lee
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L28/84
摘要： A DRAM cell capacitor is provided, having HSG (hemispherical grain) silicon disposed on a selected portion of a storage node. The capacitor resembles a solid cylindrical configuration having a top portion, a side wall, and a top edge portion sloped downward from the top portion to the side wall. HSG silicon is disposed only on the top portion and the side wall, but not on the sloped top edge portion.
摘要翻译：提供具有设置在存储节点的选定部分上的HSG（半球形晶粒）硅的DRAM单元电容器。电容器类似于具有从顶部到侧壁向下倾斜的顶部，侧壁和顶部边缘部分的实心圆柱形构造。 HSG硅仅设置在顶部和侧壁上，而不是设置在倾斜的顶部边缘部分上。

9. 发明申请

US20100270647A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CAPACITOR 审中-公开
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US20100270647A1
公开(公告)日：2010-10-28
申请号：US12779300
申请日：2010-05-13
申请人： SUNG-IL CHO , SEUNG-YOUNG SON , CHANG-JIN KANG , KEONG-KOO CHI , JI-CHUL SHIN
发明人： SUNG-IL CHO , SEUNG-YOUNG SON , CHANG-JIN KANG , KEONG-KOO CHI , JI-CHUL SHIN
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

10. 发明授权

US07736970B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US07736970B2
公开(公告)日：2010-06-15
申请号：US11869400
申请日：2007-10-09
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

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