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1. 发明授权

US4967336A High voltage bridge interface 失效
标题翻译：高压桥接口
公开(公告)号：US4967336A
公开(公告)日：1990-10-30
申请号：US484946
申请日：1990-02-26
申请人： Robert B. Davies , Warren J. Schultz , James J. Stipanuk
发明人： Robert B. Davies , Warren J. Schultz , James J. Stipanuk
IPC分类号： H02P27/06 , H02M7/5387 , H03K17/0412
CPC分类号： H02M7/5387 , H03K17/04123
摘要： A high voltage bridge interface circuit is provided for AC and brushless DC motor control having a high voltage isolation circuit and drive circuits which simplify the high voltage interface and reduce the total system integration effort. The isolation circuit provides the high voltage unilateral isolation between the control circuit and the high voltage power supply conductors, while the drive circuits improve the noise immunity at the gate termimals of the power MOSFET bridge. The high voltage bridge interface circuit is partitioned by providing the high voltage interface within one IC thereby permitting the integration of the discrete components of the power MOSFET drive circuits and simplifying the overall system integration.

2. 发明授权

US4703458A Circuit for writing bipolar memory cells 失效
标题翻译：用于写双极性存储单元的电路
公开(公告)号：US4703458A
公开(公告)日：1987-10-27
申请号：US809540
申请日：1985-12-16
申请人： James J. Stipanuk
发明人： James J. Stipanuk
IPC分类号： G11C11/411 , G11C11/416 , G11C7/00
CPC分类号： G11C11/4116 , G11C11/416
摘要： A circuit for writing bipolar memory cells is provided that reduces power dissipation by requiring only a small voltage change on the bit lines between read and write modes. The memory circuit includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. Each of the cells in a row are coupled between the first voltage terminal and a word line, and each of the cells in a column are coupled between a pair of the bit lines. A word line driver circuit is coupled between the first voltage terminal and one of the word lines of each of the rows for selectively applying voltage to the one of the word lines. A decoder circuit is coupled to the bit lines for enabling current through the bit lines. A current source is coupled between the second voltage terminal and each of the decoder circuits for sinking a read current through the bit lines of each column. A write current source is switchably coupled between the decoder circuits and the second voltage terminal for sinking a write current through the bit lines of each column.
摘要翻译：提供了一种用于写入双极存储器单元的电路，其通过仅在读取和写入模式之间的位线上仅需要较小的电压变化来降低功耗。存储电路包括第一电压端子，第二电压端子，多个字线，多个位线和多个存储器单元，其中多个存储器单元以行和列的矩阵排列。一行中的每个单元耦合在第一电压端和字线之间，并且列中的每个单元耦合在一对位线之间。字线驱动器电路耦合在第一电压端子和每行中的一条字线之间，用于选择性地将电压施加到该字线之一。解码器电路耦合到位线，以使电流通过位线。电流源耦合在第二电压端和每个解码器电路之间，用于吸收通过每列的位线的读取电流。写入电流源可切换地耦合在解码器电路和第二电压端子之间，用于吸收通过每列的位线的写入电流。

3. 发明授权

US4730277A Circuit for biasing row of memory cells 失效
标题翻译：用于偏置行存储单元的电路
公开(公告)号：US4730277A
公开(公告)日：1988-03-08
申请号：US809617
申请日：1985-12-16
申请人： James J. Stipanuk
发明人： James J. Stipanuk
IPC分类号： G11C11/415 , G11C8/08 , G11C7/00 , G11C8/00 , G11C11/34
CPC分类号： G11C8/08
摘要： A circuit for selecting a row of memory cells of an array is disclosed that reduces selection time, eliminates the need for providing a regulated voltage for biasing an active load, and utilizes the capacitive charge on the lower word line in the selection of the row. The array includes a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, wherein the plurality of memory cells are arranged in a matrix of rows and columns. Each of the cells in a row are coupled between the first voltage terminal and a word line, and each of the cells in a column are coupled between a pair of the bit lines. A word line driver circuit is coupled between bases of active load transistors in each of the memory cells in a row and the word line of that row for selecting that row of memory cells.
摘要翻译：公开了一种用于选择阵列的存储单元行的电路，其减少了选择时间，消除了提供用于偏置有源负载的稳压电压的需要，并且在该行的选择中利用下字线上的电容电荷。阵列包括第一电压端子，第二电压端子，多个字线，多个位线和多个存储器单元，其中多个存储器单元以行和列的矩阵排列。一行中的每个单元耦合在第一电压端和字线之间，并且列中的每个单元耦合在一对位线之间。字线驱动器电路耦合在一行中的每个存储器单元中的有源负载晶体管的基极之间，并且该行的字线用于选择该行存储器单元。

4. 发明授权

US4701882A Bipolar RAM cell 失效
标题翻译：双极RAM单元
公开(公告)号：US4701882A
公开(公告)日：1987-10-20
申请号：US809982
申请日：1985-12-16
申请人： Mark S. Birrittella , James J. Stipanuk
发明人： Mark S. Birrittella , James J. Stipanuk
IPC分类号： G11C11/411 , G11C11/00
CPC分类号： G11C11/4113 , G11C11/4116
摘要： A memory cell is provided having reduced read and write times, and a large current dynamic range between the standby mode and the read mode. A pair of cross-coupled NPN transistors operating in the inverse mode have their emitters coupled to a word line and their collectors coupled to receive a supply voltage by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive the supply voltage.
摘要翻译：提供具有缩短的读取和写入时间的存储单元以及待机模式和读取模式之间的大的电流动态范围。以反向模式工作的一对交叉耦合NPN晶体管的发射极分别耦合到字线，并且它们的集电极分别耦合以通过第一和第二负载接收电源电压。第一和第二NPN检测晶体管各自具有耦合到交叉耦合晶体管之一的基极的基极，分别耦合到第一和第二位线的发射极和耦合以接收电源电压的集电极。

5. 发明授权

US4697251A Bipolar RAM cell 失效
标题翻译：双极RAM单元
公开(公告)号：US4697251A
公开(公告)日：1987-09-29
申请号：US809551
申请日：1985-12-16
申请人： Mark S. Birrittella , James J. Stipanuk
发明人： Mark S. Birrittella , James J. Stipanuk
IPC分类号： G11C11/411 , G11C11/00
CPC分类号： G11C11/4116 , G11C11/4113
摘要： A memory cell is provided having reduced read and write times, and a large current differential between the standby mode and the read mode. A pair of cross-coupled NPN transistors have their emitters coupled to a lower word line and their collectors coupled to an upper word line by a first and second load, respectively. First and second NPN sense transistors each have a base coupled to the base of one of the cross-coupled transistors, an emitter coupled to a first and a second bit line, respectively, and a collector coupled to receive a supply voltage.
摘要翻译：提供具有减少的读取和写入时间的存储单元，以及待机模式和读取模式之间的大电流差分。一对交叉耦合的NPN晶体管的发射极分别与第一和第二负载耦合到低字线并且它们的集电极耦合到高字线。第一和第二NPN检测晶体管各自具有耦合到交叉耦合晶体管之一的基极的基极，分别耦合到第一和第二位线的发射极和耦合以接收电源电压的集电极。

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