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1. 发明申请

US20040125833A1 Widely wavelength tunable integrated semiconductor device and method for widely wavelength tuning semiconductor devices 有权
标题翻译：宽波长可调谐集成半导体器件及广泛调谐半导体器件的方法
公开(公告)号：US20040125833A1
公开(公告)日：2004-07-01
申请号：US10722277
申请日：2003-11-25
申请人： Interuniversitair Microelektronica Centrum , Rijksuniversiteit Gent
发明人： Gert Sarlet , Jens Buus , Roel Baets
IPC分类号： H01S003/10 , H01S005/00
CPC分类号： H01S5/06256 , H01S5/1003 , H01S5/1071 , H01S5/1209 , H01S5/1218
摘要： Alternative laser structures, which have potentially the same tuning performance as (S)SG-DBR and GCSR lasers, and a fabrication process which is similar to that of the (S)SG-DBR laser, are presented. The advantage of these structures is that the output power does not pass through a long passive region.
摘要翻译：具有与（S）SG-DBR和GCSR激光器具有潜在相同的调谐性能的替代激光器结构以及与（S）SG-DBR激光器类似的制造工艺。这些结构的优点是输出功率不通过长的被动区域。

2. 发明专利

JP2006518547A Semiconductor device obtained by the production method and such method of a semiconductor device 审中-公开
公开(公告)号：JP2006518547A
公开(公告)日：2006-08-10
申请号：JP2006502525
申请日：2004-01-16
申请人：インテルユニバルシテール、ミクロエレクトロニカ、セントラム、フェーゼットウェーInteruniversitair Microelektronica Centrum Vzw , コーニンクレッカフィリップスエレクトロニクスエヌヴィKoninklijke Philips Electronics N.V.
发明人：ディルク、エム．ノッター , ロバート、ランダー
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L29/786
CPC分类号： H01L21/823842 , Y10S438/976
摘要：この発明は、基板（１）と半導体本体（２）とを有する半導体装置（１０）であって、第一のチャネル領域（３Ａ）と第一の導体を含み且つ誘電体層（４）によりチャネル領域から分離された第一のゲート電極（３Ｂ）とを有する第一の（ＮＭＯＳ）ＦＥＴ（３）を備え、そして、第二のチャネル領域（５Ａ）と第一の導体とは異なる第二の導体を含み且つ誘電体層（４）によりチャネル領域（５Ａ）から分離された第二のゲート電極（５Ｂ）とを有する第二の（ＰＭＯＳ）ＦＥＴ（５）を備え、第一及び第二のゲート電極（３Ｂ、５Ｂ）を形成するために、誘電体層（４）が備えられた半導体本体（２）上に第一の導体層（３３）が堆積され、導体層（３３）は、その後、第一のチャネル領域（３Ａ）外部で除去され、その後、第二の導体層（５５）が半導体本体（２）上に堆積され、そして、第一の導体層（３３）が堆積される前に、誘電体層（４）上に中間層（６）が堆積される半導体装置の製造方法に関する。この発明によれば、中間層（６）のための材料として誘電体層（４）に対し選択的にエッチング可能な材料が選ばれ、そして、第一の導体層（３３）が堆積される前に、第一のチャネル領域（３Ａ）の位置で中間層（６）が除去され、そして、第一の導体層（３３）が堆積され、第一のチャネル領域（３Ａ）外部で除去された後に、そして、第二の導体層（５５）が堆積される前に、第二のチャネル領域（５Ａ）の位置で中間層（６）が除去される。従って、ＦＥＴが、簡単な方法で、且つ、それらのゲート誘電体にダメージを与えずに得られる。好ましくは、中間層（６）に対して選択的にエッチング可能なさらなる中間層（８）が中間層（６）上に堆積される。

3. 发明申请

US20040103937A1 Photovoltaic device 失效
标题翻译：光伏装置
公开(公告)号：US20040103937A1
公开(公告)日：2004-06-03
申请号：US10658114
申请日：2003-09-08
申请人： Interuniversitair Microelektronica Centrum (IMEC) , FernUniversitat Hagen
发明人： Renat Bilyalov , Alexander Ulyashin , Jef Poortmans , Wolfgang Fahrner
IPC分类号： H01L031/00
CPC分类号： H01L31/0745 , H01L31/0284 , H01L31/04 , H01L31/0747 , H01L31/077 , Y02E10/50
摘要： The present invention is related to a photovoltaic device, the device comprising a first layer of a first semiconductor material of a first conductivity type, a second layer of a second semiconductor material of the opposite conductivity type of the first layer, and a third layer of a third porous semiconductor material situated between the first layer and the second layer. The present invention also provides a method for producing the photovoltaic device.
摘要翻译：本发明涉及一种光伏器件，该器件包括第一导电类型的第一半导体材料的第一层，与第一层相反的导电类型的第二半导体材料的第二层和第三层的第三层位于第一层和第二层之间的第三多孔半导体材料。本发明还提供了一种用于制造光伏器件的方法。

4. 发明申请

US20040071878A1 Surface preparation using plasma for ALD Films 审中-公开
标题翻译：用ALD膜等离子体进行表面处理
公开(公告)号：US20040071878A1
公开(公告)日：2004-04-15
申请号：US10641954
申请日：2003-08-15
申请人： Interuniversitair Microelektronica Centrum (IMEC VZW)
发明人： Jorg Schuhmacher , Ana Martin Hoyas , Marc Schaekers , Serge Vanhaelemeersch
IPC分类号： C23C016/00 , B32B009/04
CPC分类号： H01L21/0234 , C23C14/04 , C23C16/0218 , C23C16/36 , H01L21/02118 , H01L21/02126 , H01L21/02203 , H01L21/28562 , H01L21/3121 , H01L21/32051 , H01L21/76814 , H01L21/76826 , H01L21/76843 , Y10T428/31504
摘要： An exemplary method for depositing a layer on a surface of a dielectric layer where the dielectric layer contains an organic material comprises exposing the surface of the dielectric layer to a substance, such as a substance containing nitrogen. This exposure modifies, at least, the exposed surface of the dielectric layer. The method further includes depositing a layer, such as a barrier layer, using an atomic layer deposition process on the exposed surface of the dielectric layer. In certain embodiments, exposure of the wafer to the substance containing nitrogen result in a first region of the dielectric having a first concentration of nitrogen incorporated and a second region having a second amount of nitrogen incorporated in the dielectric layer, the second concentration being higher greater than the first concentration.
摘要翻译：用于在电介质层包含有机材料的电介质层的表面上沉积层的示例性方法包括将介电层的表面暴露于诸如含氮物质的物质。该曝光至少改变了介电层的暴露表面。该方法还包括使用原子层沉积工艺在介电层的暴露表面上沉积诸如阻挡层的层。在某些实施方案中，将晶片暴露于含氮物质导致电介质的第一区域具有掺入的第一浓度的氮和第二区域，该第二区域具有并入电介质层中的第二量的氮，第二浓度更高比第一集中。

5. 发明申请

US20030235370A1 Fiber-to-waveguide coupler 有权
标题翻译：光纤至波导耦合器
公开(公告)号：US20030235370A1
公开(公告)日：2003-12-25
申请号：US10410825
申请日：2003-04-10
申请人： Interuniversitair Microelektronica Centrum (IMEC vzw) , Universiteit Gent
发明人： Dirk Taillaert , Roel Baets
IPC分类号： G02B006/26 , G02B006/34
CPC分类号： G02B6/34 , B82Y20/00 , G02B6/1225 , G02B6/125 , G02B6/30
摘要： An optical waveguide to fiber coupler comprises a substrate, a first waveguide and a second waveguide. The first and second waveguides are formed on the substrate and intersect at a right angle. A diffraction grating structure is formed at the intersection of the first and second waveguides, such that, when the coupler is physically abutted with a single mode optical fiber, in operation, a polarization split is obtained that couples orthogonal modes from the single-mode optical fiber into single identical modes in the first and second waveguides. Also, employing the coupler in optical polarization diverse applications provides for implementing a polarization insensitive photonic integrated circuit using such diffraction grating structures, such as, for example, photonic crystals.
摘要翻译：光波导到光纤耦合器包括衬底，第一波导和第二波导。第一和第二波导形成在基板上并以直角相交。衍射光栅结构形成在第一和第二波导的相交处，使得当耦合器物理地与单模光纤相接时，在操作中获得偏振分裂，其将来自单模光学光纤在第一和第二波导中成为单个相同的模式。此外，采用光学偏振多种应用中的耦合器提供了使用这种衍射光栅结构（例如光子晶体）实现偏振不敏感的光子集成电路。

6. 发明申请

US20040246472A1 Method and apparatus for defect detection 有权
标题翻译：缺陷检测方法和装置
公开(公告)号：US20040246472A1
公开(公告)日：2004-12-09
申请号：US10458405
申请日：2003-06-09
申请人： Interuniversitair Microelektronica Centrum (IMEC vzw)
发明人： Frank Holsteyns , Francesca Iacopi , Karen Maex
IPC分类号： G01N021/00
CPC分类号： H01L22/24 , G01N21/8422 , G01N21/9501
摘要： A method for determining the presence of defects in a covering layer overlying an underlying layer in accordance with an embodiment of the invention comprises providing a substrate comprising the covering layer, where the covering layer is at least partially exposed. The covering layer is subjected to a first substance, such as a solvent, and then subjected to a light beam. An optical property of the covering layer is determined and compared with a threshold value. The presence of defects in the covering layer is determined by the difference of the optical property from the threshold value, where the optical property indicates a level of penetration of the first substance through the covering layer.
摘要翻译：根据本发明的实施例的用于确定覆盖层的覆盖层中的缺陷的存在的方法包括提供包括覆盖层的基底，其中覆盖层至少部分地暴露。将覆盖层经受第一物质，例如溶剂，然后经受光束。确定覆盖层的光学特性并将其与阈值进行比较。覆盖层中的缺陷的存在由光学性质与阈值的差异决定，其中光学特性表示第一物质穿过覆盖层的穿透水平。

7. 发明申请

US20040028952A1 High dielectric constant composition and method of making same 有权
标题翻译：高介电常数组成及其制作方法
公开(公告)号：US20040028952A1
公开(公告)日：2004-02-12
申请号：US10459360
申请日：2003-06-10
申请人： Interuniversitair Microelektronica Centrum (IMEC vzw)
发明人： Eduard Cartier , Jerry Chen , Chao Zhao
IPC分类号： B32B009/00 , C23C016/00
CPC分类号： H01L21/28185 , C01G27/02 , C01P2002/72 , C23C16/40 , C23C16/405 , C23C16/4412 , H01B3/10 , H01L21/28167 , H01L21/28194 , H01L21/31604 , H01L28/40 , H01L29/517 , H01L29/518 , Y10T428/24917 , Y10T428/265
摘要： Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.
摘要翻译：公开了包含HfO 2和第二化合物的介电材料组合物。组合物的特征在于至少一部分组合物为立方晶相。此外，公开了包含这种介电材料化合物的基于半导体的器件及其形成方法。

8. 发明申请

US20040233694A1 Single bit nonvolatile memory cell and methods for programming and erasing thereof 失效
标题翻译：单位非易失性存储单元及其编程和擦除方法
公开(公告)号：US20040233694A1
公开(公告)日：2004-11-25
申请号：US10680878
申请日：2003-10-07
申请人： Interuniversitair Microelektronica Centrum (IMEC vzw) , Infineon AG
发明人： Gang Xue , Jan Van Houdt
IPC分类号： G11C011/22
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26
摘要： A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.
摘要翻译：一种用于编程集成在金属 - 电介质 - 半导体技术芯片上的单个位非易失性存储单元的方法。存储单元包括在源极和漏极之间包括源极，漏极和沟道的半导体衬底。该存储单元还包括一个包括栅电极和电介质叠层的控制栅极。栅极通过电介质堆叠与沟道分离。此外，电介质叠层包括至少一个电荷存储电介质层。用于对存储单元进行编程的方法包括将电接地施加到源极，向漏极施加具有第一极性的第一电压，将第一极性的第二电压施加到控制栅极; 以及将具有与所述第一极性相反的第二极性的第三电压施加到所述半导体衬底。

9. 发明申请

US20040018532A1 Electronic sensor device 审中-公开
标题翻译：电子传感器装置
公开(公告)号：US20040018532A1
公开(公告)日：2004-01-29
申请号：US10454765
申请日：2003-06-03
申请人： Interuniversitair Microelektronica Centrum (IMEC)
发明人： Filip Frederix
IPC分类号： C12Q001/68 , C12M001/34
CPC分类号： C07D207/404 , B05D1/185 , B82Y30/00 , B82Y40/00 , G01N33/54353 , G01N33/54393
摘要： The present invention is related to a device suitable for the preparation of a sensor, comprising a substrate comprising a metal layer, the metal layer comprising at least a first region wherein to a first region is attached a first species comprising a compound of chemical formula: XnullR1nullSnullSnullR2nullY wherein R1 and R2 represent independently from each other spacer of n carbon atoms, n being an integer higher than 11; wherein X represents: 1 and Y represents an organic group. The first species is able to form a self-assembling monolayer on the first region.
摘要翻译：本发明涉及一种适用于制备传感器的装置，包括一个包括一个金属层的基底，该金属层至少包括一个第一区域，其中一个第一区域附着有第一个物质，该物质包含化学式为： X-R1-SS-R2-Y其中R1和R2彼此独立地表示n个碳原子的间隔基，n是高于11的整数; 其中X表示：和Y表示有机基团。第一种能够在第一区域形成自组装单层。

10. 发明申请

US20030209754A1 Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure 审中-公开
公开(公告)号：US20030209754A1
公开(公告)日：2003-11-13
申请号：US10424193
申请日：2003-04-25
申请人： Interuniversitair Microelektronica Centrum (IMEC)
发明人： Luc Haspeslagh
IPC分类号： H01L029/76
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/0483 , H01L29/40114 , H01L29/40117 , H01L29/7923
摘要： A planar high-density EEPROM split gate memory structure, is formed using two poly-layers and chemical-mechanical-polishing processes. Stripes of contiguous poly lines, alternately formed in one of the two poly-layers, constitute the memory structure. Source and drain regions are formed self-aligned to the outer borders of this memory structure. Depending on the biasing scheme a poly line is used as the select gate of the memory cell while an adjacent poly line is used as program gate, so to have charge stored underneath this adjacent poly line using source-side-injection of charge carriers. The other poly lines are biased to form conductive channels between the select and program gate to the source and drain regions. These conductive channels form soft source and drain regions next to the select and program gate in use.

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