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1. 发明专利

DD253362A3 未知
公开(公告)号：DD253362A3
公开(公告)日：1988-01-20
申请号：DD25031483
申请日：1983-04-29
申请人： BLOCH EVGENIJ M , GORBACHEV OLEG S , IOFFE ANATOLIJ F , PETROV ALEKSEJ O , PETROVA NATALIJA N , CHORIN VLADIMIR S
发明人： BLOCH EVGENIJ M , GORBACEV OLEG S , IOFFE ANATOLIJ F , PETROV ALEKSEJ O , PETROVA NATALIJA N , CHORIN VLADIMIR S
IPC分类号： G09G1/16

2. 发明专利

SU1345185A1 DEVICE FOR INTERFACING MICROCOMPUTER WITH CASSETTE TAPE RECORDER 未知
公开(公告)号：SU1345185A1
公开(公告)日：1987-10-15
申请号：SU3417020
申请日：1982-04-05
申请人： GORBACHEV OLEG S , IOFFE ANATOLIJ F , KULAGIN MIKHAIL V , RUVINSKIJ BORIS , KHORIN VLADIMIR S , CHUGUNOV YURIJ V
发明人： GORBACHEV OLEG S , IOFFE ANATOLIJ F , KULAGIN MIKHAIL V , RUVINSKIJ BORIS I , KHORIN VLADIMIR S , CHUGUNOV YURIJ V
IPC分类号： G06F13/00 , G06F3/00

3. 发明专利

FI850010L 未知
公开(公告)号：FI850010L
公开(公告)日：1986-07-03
申请号：FI850010
申请日：1985-01-02
申请人： BLOKH EVGENY MOISEEVICH , GORBACHEV OLEG S , IOFFE ANATOLIJ F , PETROV ALEXEI O , PETROVA NATALIA N , KHORIN VLADIMIR SERGEEVICH
发明人： BLOKH EVGENY MOISEEVICH , GORBACHEV OLEG SEMENOVICH , IOFFE ANATOLY FEDOROVICH , PETROV ALEXEI OLEGOVICH , PETROVA NATALIA NIKOLAEVNA , KHORIN VLADIMIR SERGEEVICH
IPC分类号： G06F20060101 , G06F

4. 发明专利

GB2169178A Display processor 未知
公开(公告)号：GB2169178A
公开(公告)日：1986-07-02
申请号：GB8432790
申请日：1984-12-31
申请人： GORBACHEV OLEG S , IOFFE ANATOLIJ F , TORGOV JURY IGOREVICH , KHORIN VLADIMIR SERGEEVICH , PETROV ALEXI OLEGOVICH , PETROVA NATALIA N
发明人： GORBACHEV OLEG SEMENOVICH , IOFFE ANATOLY FEDOROVICH , TORGOV JURY IGOREVICH , KHORIN VLADIMIR SERGEEVICH , PETROV ALEXI OLEGOVICH , PETROVA NATALIA NIKOLAEVNA
IPC分类号： G09G5/42 , G09G1/16 , G06F3/153
摘要： A display processor comprises several inter-connected elements: units (1) and (2) or comparing the desired and current X and Y coordinates, X and Y coordinate search units (5) and (6), an address multiplexer (17), a RAM (20), a multichannel switch (21), an image character analysing unit (25) and a video adder (27). The address multiplexer (17) is connected to an Y coordinate search unit (6) and the image character analysing unit (25). The multichannel switch (21) is connected to the units (1) and (2) and to the adder (27). The data input is to the switch (21), the address input to multiplexer (17) and the video output is taken from adder (27). Control inputs enter at (10), (13), (39), (41).

6. 发明专利

SU800902A1 METHOD OF DETERMINING SIGNAL-TO-NOISE RATIO 未知
公开(公告)号：SU800902A1
公开(公告)日：1981-01-30
申请号：SU2736077
申请日：1979-03-11
申请人： ZABOLOTSKIJ VADIM P , BALASHOV VYACHESLAV Z , IOFFE ANATOLIJ YA , MOROZOV LEV M , IOFFE SERGEJ A
发明人： ZABOLOTSKIJ VADIM P , BALASHOV VYACHESLAV Z , IOFFE ANATOLIJ YA , MOROZOV LEV M , IOFFE SERGEJ A
IPC分类号： G01R29/26

7. 发明专利

SU708414A2 DEVICE FOR RETRIEVAL INFORMATION FROM STORAGE UNITS 未知
公开(公告)号：SU708414A2
公开(公告)日：1980-01-05
申请号：SU2632336
申请日：1978-06-22
申请人： IOFFE ANATOLIJ F , KRUPSKIJ ALEKSANDR A
发明人： IOFFE ANATOLIJ F , KRUPSKIJ ALEKSANDR A
IPC分类号： G11C8/02

8. 发明专利

SU639050A1 SEMICONDUCTOR DEVICE SECURING ASSEMBLY 未知
公开(公告)号：SU639050A1
公开(公告)日：1978-12-25
申请号：SU2473930
申请日：1977-04-06
申请人： IOFFE ANATOLIJ YA , OKUN MIKHAIL Z , ROZENBLIT ROMAN A
发明人： IOFFE ANATOLIJ YA , OKUN MIKHAIL Z , ROZENBLIT ROMAN A
IPC分类号： H01L23/34

9. 发明专利

IT1188505B Video display processor 未知
公开(公告)号：IT1188505B
公开(公告)日：1988-01-14
申请号：IT4150285
申请日：1985-01-24
申请人： GORBACHEV OLEG S , IOFFE ANATOLIJ F , PETROV ALEXEI O , PETROVA NATALIA N , TORGOV JURY IGOREVICH , KHORIN VLADIMIR SERGEEVICH
发明人： GORBACHEV OLEG SEMENOVICH , IOFFE ANATOLY FEDOROVICH , PETROV ALEXEI OLEGOVICH , PETROVA NATALIA NIKOLAEVNA , TORGOV JURY IGOREVICH , KHORIN VLADIMIR SERGEEVICH
IPC分类号： G02B20060101 , G02B
摘要： The processor comprises units for comparing the prescribed and current X and Y coordinates, whose control inputs are the control inputs of the processor and which are electrically connected with a random-access memory connected in series with a multi-channel switch. One input of the switch is the information input of the processor. A video adder has one input as the control input of the processor. Additionally included is a pattern line sequencing unit whose one input is coupled to the output of the multichannel switch, while three other inputs are respective control inputs of the processor, a Y coordinate search unit whose one input is coupled to the unit for comparing the prescribed and current Y coordinates, while the other input is one of the control inputs of the processor. An address multiplexer has one input as the address input of the processor, the next two inputs connected to the pattern line sequencing unit. Two other inputs are connected to the Y co-ordinate search unit and one more input is connected both to the pattern line sequencing unit and to the Y coordinate search unit while the output is connected to the random-access memory. A pattern analysing unit has one input as the control input of the processor, two other inputs and one output connected to the multichannel switch, another output is connected to one more input of the pattern line sequencing unit, another output is connected to the video adder, to the multichannel switch and to one more input of the address multiplexer. This is connected to one more output of the pattern analysing unit. The multichannel switch is coupled to one more input of the unit for comparing the prescribed and current X and Y coordinates and of the video adder, while the output of the unit is coupled to one more input of the video adder.

10. 发明专利

DE3500404A1 Display processor 未知
公开(公告)号：DE3500404A1
公开(公告)日：1986-07-10
申请号：DE3500404
申请日：1985-01-08
申请人： GORBACEV OLEG SEMENOVIC , IOFFE ANATOLIJ F , PETROV ALEKSEJ OLEGOVIC , PETROVA NATALIJA NIKOLAEVNA , TORGOV JURIJ IGOREVIC , CHORIN VLADIMIR SERGEEVIC
发明人： GORBACEV OLEG SEMENOVIC , IOFFE ANATOLIJ FEDOROVIC , PETROV ALEKSEJ OLEGOVIC , PETROVA NATALIJA NIKOLAEVNA , TORGOV JURIJ IGOREVIC , CHORIN VLADIMIR SERGEEVIC
IPC分类号： G09G5/42 , G06F3/153
摘要： The display processor comprises the following sub-assemblies, interconnected to one another in series: a set-X and actual-X coordinate comparator (1), an X-coordinate selector (5), an address multiplexer (17), a random-access memory (20), a multi-channel changeover switch (21), a symbol image analyser (25) and a video summer (27). Connected to the address multiplexer (17) is a Y-coordinate selector (6), to which a set-Y and actual-Y coordinate comparator (2) and the symbol image analyser (25) are connected. The multi-channel changeover switch (21) is connected to the set-X and actual-X coordinate comparator (1), to the set-Y and actual-Y coordinate comparator (2) and to the video summer (27).

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