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1. 发明申请

US20090061811A1 MULTI-FREQUENCY SYNTHESIZING APPARATUS AND METHOD FOR MULTI-BAND RF RECEIVER 有权
标题翻译：用于多频RF接收机的多频合成装置和方法
公开(公告)号：US20090061811A1
公开(公告)日：2009-03-05
申请号：US12262234
申请日：2008-10-31
申请人： Eun Chul Park , Hyun Soo Chae , Hoon Tae Kim
发明人： Eun Chul Park , Hyun Soo Chae , Hoon Tae Kim
IPC分类号： H04B1/26 , H03B21/00
CPC分类号： H04B1/0082 , H03B21/02
摘要： A frequency synthesizing apparatus and method for a multi-band radio frequency (RF) receiver is provided. The frequency synthesizing apparatus includes a simple circuit configuration with a single SSB mixer and thus, may synthesize six high frequency signals. Signals to be inputted into the SSB mixer include a first signal and a second signal. The first signal is generated based on a VCO and a PPF. Also, the second signal is selected from a plurality of frequency divided signals which are generated by dividing a signal generated in the VCO via a plurality of dividers.
摘要翻译：提供了一种用于多频带射频（RF）接收机的频率合成装置和方法。频率合成装置包括具有单个SSB混频器的简单电路配置，因此可以合成六个高频信号。要输入到SSB混频器的信号包括第一信号和第二信号。基于VCO和PPF产生第一信号。而且，第二信号是通过经由多个分频器划分在VCO中产生的信号而产生的多个分频信号中选择的。

2. 发明授权

US07701300B2 Multi-frequency synthesizing apparatus and method for multi-band RF receiver 有权
公开(公告)号：US07701300B2
公开(公告)日：2010-04-20
申请号：US11481964
申请日：2006-07-07
申请人： Eun Chul Park , Hyun Soo Chae , Hoon Tae Kim
发明人： Eun Chul Park , Hyun Soo Chae , Hoon Tae Kim
IPC分类号： H03B21/01 , H04B1/26
CPC分类号： H04B1/0082 , H03B21/02
摘要： A frequency synthesizing apparatus and method for a multi-band radio frequency (RF) receiver is provided. The frequency synthesizing apparatus includes a simple circuit configuration with a single SSB mixer and thus, may synthesize six high frequency signals. Signals to be inputted into the SSB mixer include a first signal and a second signal. The first signal is generated based on a VCO and a PPF. Also, the second signal is selected from a plurality of frequency divided signals which are generated by dividing a signal generated in the VCO via a plurality of dividers.

3. 发明授权

US07668263B2 Multi-frequency synthesizing apparatus and method for multi-band RF receiver 有权
标题翻译：多频RF接收机的多频合成装置及方法
公开(公告)号：US07668263B2
公开(公告)日：2010-02-23
申请号：US12262234
申请日：2008-10-31
申请人： Eun Chul Park , Hyun Soo Chae , Hoon Tae Kim
发明人： Eun Chul Park , Hyun Soo Chae , Hoon Tae Kim
IPC分类号： H04L27/04 , H03D1/24
CPC分类号： H04B1/0082 , H03B21/02
摘要： A frequency synthesizing apparatus and method for a multi-band radio frequency (RF) receiver is provided. The frequency synthesizing apparatus includes a simple circuit configuration with a single SSB mixer and thus, may synthesize six high frequency signals. Signals to be inputted into the SSB mixer include a first signal and a second signal. The first signal is generated based on a VCO and a PPF. Also, the second signal is selected from a plurality of frequency divided signals which are generated by dividing a signal generated in the VCO via a plurality of dividers.
摘要翻译：提供了一种用于多频带射频（RF）接收机的频率合成装置和方法。频率合成装置包括具有单个SSB混频器的简单电路配置，因此可以合成六个高频信号。要输入到SSB混频器的信号包括第一信号和第二信号。基于VCO和PPF产生第一信号。而且，第二信号是通过经由多个分频器划分在VCO中产生的信号而产生的多个分频信号中选择的。

4. 发明授权

US08067968B2 Locking state detector and DLL circuit having the same 有权
标题翻译：具有相同的锁定状态检测器和DLL电路
公开(公告)号：US08067968B2
公开(公告)日：2011-11-29
申请号：US12890169
申请日：2010-09-24
申请人： Dong-Suk Shin , Chul Woo Kim , Hyun Soo Chae
发明人： Dong-Suk Shin , Chul Woo Kim , Hyun Soo Chae
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/095
摘要： A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.
摘要翻译：锁定状态检测器包括：相位比较单元，被配置为比较参考时钟信号和反馈时钟信号以产生第一相位差区分信号以区分第一相位差范围;以及第二相位差区别信号，以区分第二相位差范围宽于第一相位差范围;锁定状态设置单元，被配置为响应于第一相位差识别信号和第二相位差识别信号产生锁定状态信号。

5. 发明授权

US07839190B2 Locking state detector and DLL circuit having the same 有权
标题翻译：具有相同的锁定状态检测器和DLL电路
公开(公告)号：US07839190B2
公开(公告)日：2010-11-23
申请号：US12263300
申请日：2008-10-31
申请人： Dong-Suk Shin , Chul Woo Kim , Hyun Soo Chae
发明人： Dong-Suk Shin , Chul Woo Kim , Hyun Soo Chae
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/095
摘要： A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.
摘要翻译：锁定状态检测器包括：相位比较单元，被配置为比较参考时钟信号和反馈时钟信号以产生第一相位差区分信号以区分第一相位差范围;以及第二相位差区别信号，以区分第二相位差范围宽于第一相位差范围;锁定状态设置单元，被配置为响应于第一相位差识别信号和第二相位差识别信号产生锁定状态信号。

6. 发明授权

US07548124B2 System and method for self calibrating voltage-controlled oscillator 有权
标题翻译：用于自校准压控振荡器的系统和方法
公开(公告)号：US07548124B2
公开(公告)日：2009-06-16
申请号：US11586655
申请日：2006-10-26
申请人： Hyun Soo Chae , Jung Eun Lee , Chun Deok Suh , Hoon Tae Kim
发明人： Hyun Soo Chae , Jung Eun Lee , Chun Deok Suh , Hoon Tae Kim
IPC分类号： H03L7/113
CPC分类号： H03L7/087 , H03L7/099 , H03L7/193 , H03L2207/06
摘要： A system and a method for self calibrating a voltage-controlled oscillator (VCO). In the system, a mode controller generates a control signal for each of an automatic band selection mode, an automatic gain tuning mode, and a phase-locking mode, from a frequency comparison result between a reference clock signal and a divided clock signal which is generated by dividing a frequency of an oscillation signal, and thereby controls the VCO, so that the VCO may generate the oscillation signal which is automatically phase-locked in a target frequency with an optimal state.
摘要翻译：一种用于自校准压控振荡器（VCO）的系统和方法。在该系统中，模式控制器根据参考时钟信号和分频时钟信号之间的频率比较结果，生成自动频带选择模式，自动增益调谐模式和锁相模式中的每一个的控制信号通过分频振荡信号产生，从而控制VCO，使得VCO可以产生具有最佳状态的目标频率中自动锁相的振荡信号。

7. 发明申请

US20070249293A1 System and method for self calibrating voltage-controlled oscillator 有权
标题翻译：用于自校准压控振荡器的系统和方法
公开(公告)号：US20070249293A1
公开(公告)日：2007-10-25
申请号：US11586655
申请日：2006-10-26
申请人： Hyun Soo Chae , Jung Eun Lee , Chun Deok Suh , Hoon Tae Kim
发明人： Hyun Soo Chae , Jung Eun Lee , Chun Deok Suh , Hoon Tae Kim
IPC分类号： H04B1/40 , H04B1/06 , H04B7/00
CPC分类号： H03L7/087 , H03L7/099 , H03L7/193 , H03L2207/06
摘要： A system and a method for self calibrating a voltage-controlled oscillator (VCO). In the system, a mode controller generates a control signal for each of an automatic band selection mode, an automatic gain tuning mode, and a phase-locking mode, from a frequency comparison result between a reference clock signal and a divided clock signal which is generated by dividing a frequency of an oscillation signal, and thereby controls the VCO, so that the VCO may generate the oscillation signal which is automatically phase-locked in a target frequency with an optimal state.
摘要翻译：一种用于自校准压控振荡器（VCO）的系统和方法。在该系统中，模式控制器根据参考时钟信号和分频时钟信号之间的频率比较结果，生成自动频带选择模式，自动增益调谐模式和锁相模式中的每一个的控制信号通过分频振荡信号产生，从而控制VCO，使得VCO可以产生具有最佳状态的目标频率中自动锁相的振荡信号。

8. 发明授权

US06694105B2 Burst mode receiving apparatus having an offset compensating function and a data recovery method thereof 失效
标题翻译：具有偏移补偿功能的突发模式接收装置及其数据恢复方法
公开(公告)号：US06694105B2
公开(公告)日：2004-02-17
申请号：US10183046
申请日：2002-06-27
申请人： Young-jun Chang , Hyun-soo Chae , Gun-hee Han , Hyun-surk Ryu
发明人： Young-jun Chang , Hyun-soo Chae , Gun-hee Han , Hyun-surk Ryu
IPC分类号： H04B1006
CPC分类号： H04L25/061
摘要： A burst mode receiving apparatus having an offset compensating function and a data recovery method thereof, including an intermediate value detector to detect and output an intermediate value of an input signal input from an outside source in response to a switching control signal; an amplifier to amplify and output a difference between the input signal and a reference value; an offset compensator to generate a compensation signal having a level varied corresponding to the amplified result input from the amplifier and a compensation control signal; a summing portion to add the compensation signal and the intermediate value to output the added result as the reference value to the amplifier; and a controller to generate the switching control signal and the compensation control signal corresponding to a result obtained by analyzing the amplified result input from the amplifier and a reset signal input from the outside source.
摘要翻译：一种具有偏移补偿功能的突发模式接收装置及其数据恢复方法，包括：中间值检测器，用于响应于切换控制信号检测并输出从外部源输入的输入信号的中间值; 放大器，用于放大和输出输入信号和参考值之间的差; 偏移补偿器，用于产生具有对应于从放大器输入的放大结果变化的电平的补偿信号和补偿控制信号; 加法部分，用于将补偿信号和中间值相加以将相加结果作为参考值输出到放大器; 以及控制器，用于产生对应于通过分析从放大器输入的放大结果和从外部源输入的复位信号而获得的结果的开关控制信号和补偿控制信号。

9. 发明申请

US20110012654A1 LOCKING STATE DETECTOR AND DLL CIRCUIT HAVING THE SAME 有权
标题翻译：锁定状态检测器和具有相同功能的DLL电路
公开(公告)号：US20110012654A1
公开(公告)日：2011-01-20
申请号：US12890169
申请日：2010-09-24
申请人： Dong Suk Shin , Chul Woo Kim , Hyun Soo Chae
发明人： Dong Suk Shin , Chul Woo Kim , Hyun Soo Chae
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/095
摘要： A locking state detector includes a phase comparing unit configured to compare a reference clock signal and a feedback clock signal to generate a first phase difference distinction signal to distinguish a first phase difference range, and a second phase difference distinction signal to distinguish a second phase difference range wider than the first phase difference range, and a locking state setting unit configured to generate a locking state signal in response to the first phase difference distinction signal and the second phase difference distinction signal.
摘要翻译：锁定状态检测器包括：相位比较单元，被配置为比较参考时钟信号和反馈时钟信号以产生第一相位差区分信号以区分第一相位差范围;以及第二相位差区别信号，以区分第二相位差范围宽于第一相位差范围;锁定状态设置单元，被配置为响应于第一相位差识别信号和第二相位差识别信号产生锁定状态信号。

10. 发明授权

US07453317B2 Apparatus and method for reducing flicker noise of CMOS amplifier 有权
标题翻译：降低CMOS放大器闪烁噪声的装置和方法
公开(公告)号：US07453317B2
公开(公告)日：2008-11-18
申请号：US11645742
申请日：2006-12-27
申请人： Jeong Wook Koh , Hyun Soo Chae , Hoon Tae Kim
发明人： Jeong Wook Koh , Hyun Soo Chae , Hoon Tae Kim
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/26
摘要： An apparatus and method of reducing a flicker noise of a CMOS amplifier is provided. In the CMOS amplifier, a load circuit is connected to a signal input circuit which includes two pairs of MOSFETs which simultaneously receive differential signals. In this instance, a first MOSFET included in a switch-bias circuit is connected to one pair of MOSFETs which receive the differential signals and functions as a current source in the case of activation of a clock signal Ø1. A second MOSFET included in the switch-bias circuit is connected to another pair of MOSFETs which receive the differential signals and functions as a current source in the case of activation of a clock signal Ø2.
摘要翻译：提供了降低CMOS放大器的闪烁噪声的装置和方法。在CMOS放大器中，负载电路连接到信号输入电路，该信号输入电路包括同时接收差分信号的两对MOSFET。在这种情况下，包括在开关偏置电路中的第一MOSFET连接到一对MOSFET，它们在激活时钟信号φ1的情况下接收差分信号并用作电流源。包括在开关偏置电路中的第二个MOSFET连接到另一对MOSFET，它们在启动时钟信号Ø2的情况下接收差分信号并用作电流源。

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