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1. 发明申请

US20070077709A1 SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED CONTACT HOLE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有自对准接触孔的半导体器件及其制造方法
公开(公告)号：US20070077709A1
公开(公告)日：2007-04-05
申请号：US11463814
申请日：2006-08-10
申请人： Hyoung-Sub KIM
发明人： Hyoung-Sub KIM
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/76831 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10873 , H01L27/10888 , H01L27/10894
摘要： According to embodiments of the invention, word line patterns are placed on a semiconductor substrate in a cell array region and at least one gate pattern is placed on the semiconductor substrate in a peripheral circuit region. Side walls of the word line patterns and the gate pattern are covered with word line spacers and gate spacers having the same width as that of the word line spacers, respectively. The semiconductor substrate having the word line spacers and the gate spacers is covered with an interlayer insulating layer. A self-aligned contact hole formed in the interlayer insulating layer penetrates a predetermined region between the word line patterns. The self-aligned contact hole is formed by etching the interlayer insulating layer and the word line spacers. The side walls of the self-aligned contact hole are covered with a self-aligned contact spacer having a width different from that of the gate spacers.
摘要翻译：根据本发明的实施例，字线图形被放置在单元阵列区域中的半导体衬底上，并且至少一个栅极图案被放置在外围电路区域中的半导体衬底上。字线图案和栅极图案的侧壁分别用与字线间隔件宽度相同的字线间隔物和栅极间隔物覆盖。具有字线间隔物和栅极间隔物的半导体衬底被层间绝缘层覆盖。形成在层间绝缘层中的自对准接触孔穿过字线图案之间的预定区域。通过蚀刻层间绝缘层和字线间隔物形成自对准接触孔。自对准接触孔的侧壁被具有与栅极间隔物的宽度不同的宽度的自对准接触间隔物覆盖。

2. 发明申请

US20050001252A1 Semiconductor device with trench gate type transistor and method of manufacturing the same 有权
标题翻译：具有沟槽栅型晶体管的半导体器件及其制造方法
公开(公告)号：US20050001252A1
公开(公告)日：2005-01-06
申请号：US10858727
申请日：2004-06-02
申请人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Myeong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
发明人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Myeong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876 , H01L29/7834
摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
摘要翻译：半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁，活动区域延伸的第二方向。隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

3. 发明授权

US06218690B1 Transistor having reverse self-aligned structure 有权
标题翻译：晶体管具有反向自对准结构
公开(公告)号：US06218690B1
公开(公告)日：2001-04-17
申请号：US09376041
申请日：1999-08-16
申请人： Hyoung-sub Kim , Ja-hum Ku , Chul-sung Kim , Jung-woo Park
发明人： Hyoung-sub Kim , Ja-hum Ku , Chul-sung Kim , Jung-woo Park
IPC分类号： H01L2976
CPC分类号： H01L29/66606 , H01L29/66621
摘要： A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the semiconductor substrate, the drain being positioned a predetermined distance from the source. A silicide film is formed on the source and the drain. Insulative film spacers are formed on sidewalls of a trench, the trench being formed by etchin the semiconductor substrate between the source and the drain. A gate insulative film is formed on a lower portion of the trench and a metal gate is formed on the gate insulative film between the insulative film spacers. The metal gate is electrically isolated from the source and the drain by the insulative film spacers.
摘要翻译：提供了反向自对准场效应晶体管及其制造方法。反向自对准晶体管包括形成在半导体衬底的有源区上的源极和形成在半导体衬底的有源区上的漏极，漏极位于与源极预定的距离处。在源极和漏极上形成硅化物膜。绝缘膜间隔物形成在沟槽的侧壁上，沟槽通过蚀刻在源极和漏极之间的半导体衬底形成。栅极绝缘膜形成在沟槽的下部，并且在绝缘膜间隔物上的栅极绝缘膜上形成金属栅极。金属栅极通过绝缘膜间隔物与源极和漏极电隔离。

4. 发明申请

US20150132942A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING BURIED CONTACTS AND RELATED SEMICONDUCTOR DEVICES 有权
标题翻译：制造带有接触触点的半导体器件和相关半导体器件的方法
公开(公告)号：US20150132942A1
公开(公告)日：2015-05-14
申请号：US14538832
申请日：2014-11-12
申请人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Ji-young Kim
发明人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Ji-young Kim
IPC分类号： H01L21/768 , H01L21/321 , H01L21/3205 , H01L21/311
CPC分类号： H01L27/10823 , H01L21/31111 , H01L21/31144 , H01L21/76224 , H01L23/5226 , H01L23/528 , H01L23/53295 , H01L27/10814 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10891
摘要： Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：通过在第一方向上布置的第一槽形成位线结构，该第一槽在第一方向上延伸，并且在垂直于第一方向的第二方向上彼此间隔开，在其中掩埋有字线的衬底上; 在位线结构的两个侧壁上形成多层间隔物; 形成牺牲层以填充第一凹槽; 通过图案化牺牲层形成在第一方向和第二方向上彼此间隔开的第二凹槽; 蚀刻位于第二凹槽中的多层间隔物的最外层间隔; 在第二槽中形成第一辅助间隔件; 形成绝缘层以填充第二凹槽; 以及通过去除牺牲层和绝缘层，在第一辅助隔离物的两侧上，在第一方向和第二方向上形成彼此间隔开的第三槽。

5. 发明授权

US09012321B1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09012321B1
公开(公告)日：2015-04-21
申请号：US14283666
申请日：2014-05-21
申请人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Nak-jin Son , Ji-young Kim
发明人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Nak-jin Son , Ji-young Kim
IPC分类号： H01L21/00 , H01L21/762 , H01L21/768
CPC分类号： H01L21/76224 , H01L21/743 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成牺牲膜作为形成半导体器件的工艺的一部分。牺牲膜相对于半导体器件的其它材料具有相对高的蚀刻选择性，以便减少蚀刻掩模的损耗并提高半导体器件的部件（例如，埋入触点）的质量。

6. 发明申请

US20110017990A1 Thin-film transistor and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20110017990A1
公开(公告)日：2011-01-27
申请号：US12659153
申请日：2010-02-26
申请人： Kyoung-seok Son , Jang-yeon Kwon , Hyoung-sub Kim , Hoo-jeong Lee , Mi-ran Moon , Kyung Park
发明人： Kyoung-seok Son , Jang-yeon Kwon , Hyoung-sub Kim , Hoo-jeong Lee , Mi-ran Moon , Kyung Park
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869
摘要： Example embodiments relate to thin-film transistors (TFT) and methods for fabricating the same. A thin-film transistor according to example embodiments may include a gate, a gate insulation layer, a channel layer including a first oxide semiconductor layer and a second oxide semiconductor layer, and a source and drain on opposite sides of the channel layer. The first oxide semiconductor layer may have relatively large crystal grains compared to the second oxide semiconductor layer.
摘要翻译：示例性实施例涉及薄膜晶体管（TFT）及其制造方法。根据示例性实施例的薄膜晶体管可以包括栅极，栅极绝缘层，包括第一氧化物半导体层和第二氧化物半导体层的沟道层，以及在沟道层的相对侧上的源极和漏极。与第二氧化物半导体层相比，第一氧化物半导体层可以具有相对较大的晶粒。

7. 发明授权

US07057242B2 Transistor structures having access gates with narrowed central portions 有权
公开(公告)号：US07057242B2
公开(公告)日：2006-06-06
申请号：US10264136
申请日：2002-10-03
申请人： Ji-young Kim , Hyoung-sub Kim
发明人： Ji-young Kim , Hyoung-sub Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/10873 , H01L21/28123 , H01L27/0207 , H01L29/1033 , H01L29/4238
摘要： An integrated circuit transistor includes an active region in a substrate, elongated along a first direction. A gate pattern is disposed on the substrate and crosses the active region along a second direction transverse to the first direction. The gate pattern includes an access gate portion disposed on the active region and narrowed at a central portion thereof. The gate pattern may further include a pass gate portion adjoining the access gate portion at the point beyond the edge of the active region, the pass gate portion having a lesser extent along the first direction than the access gate portion.

8. 发明申请

US20050014338A1 Integration method of a semiconductor device having a recessed gate electrode 有权
公开(公告)号：US20050014338A1
公开(公告)日：2005-01-20
申请号：US10649262
申请日：2003-08-26
申请人： Ji-Young Kim , Hyoung-Sub Kim
发明人： Ji-Young Kim , Hyoung-Sub Kim
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/8234 , H01L27/108 , H01L29/423 , H01L29/80
CPC分类号： H01L21/823456 , H01L21/823437 , H01L27/10876 , H01L27/10891 , H01L27/10894 , H01L27/10897
摘要： Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

9. 发明授权

US06696722B1 Storage node of DRAM cell 失效
标题翻译： DRAM单元的存储节点
公开(公告)号：US06696722B1
公开(公告)日：2004-02-24
申请号：US09708957
申请日：2000-11-08
申请人： Hyoung-Sub Kim
发明人： Hyoung-Sub Kim
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L21/32137 , H01L21/76895 , H01L28/60
摘要： A storage node of a DRAM cell capacitor includes a first insulating layer in which a bit line pattern is formed, a second insulating layer formed on the first insulating layer of which material is different from that of the second insulating layer, a first conductive layer formed on the second insulating layer that has an etching rate different from that of the first conductive layer, a material layer formed on the first conductive layer, which has a smaller width than the first conductive layer and is made of material with different etching characteristics from that of the first conductive layer, a second conductive layer that is formed on the material layer and has the same width as that of the material layer, and a sidewall conductive spacer that is an contact with the second conductive layer and the material layer and is formed on the top surface of the first conductive layer and on sides of the material layer and the second conductive layer.
摘要翻译： DRAM单元电容器的存储节点包括其中形成位线图形的第一绝缘层，形成在与第二绝缘层的材料不同的第一绝缘层上的第二绝缘层，形成的第一导电层在具有与第一导电层不同的蚀刻速率的第二绝缘层上，形成在第一导电层上的材料层，其宽度小于第一导电层，并且由与第一导电层不同的蚀刻特性的材料制成形成在所述材料层上并且具有与所述材料层的宽度相同的宽度的第二导电层，以及与所述第二导电层和所述材料层接触形成的侧壁导电间隔物，在第一导电层的顶表面上以及材料层和第二导电层的侧面上。

10. 发明授权

US11439222B2 Shampoo assisting device 有权
公开(公告)号：US11439222B2
公开(公告)日：2022-09-13
申请号：US17041048
申请日：2020-07-15
申请人： Hyoung-Sub Kim
发明人： Hyoung-Sub Kim
IPC分类号： A45D44/10 , A45D19/00 , A45D19/10 , A47K3/12
摘要： The proposed is directed to a shampoo assisting device that is mounted on a wash basin, a bathtub, a sink, etc. with a simple configuration to allow the user to be shampooed while lying down. The shampoo assisting device includes a main body having a locking part provided on one side and a headrest part provided on the other side to support a user's head, and a first support protruding from a lower portion of the main body so as to be closely supported by a bottom surface of a wash basin.

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