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1. 发明专利

TWI264116B 薄膜記憶體,陣列,和其操作方法及製造方法 THIN FILM MEMORY, ARRAY, AND OPERATION METHOD AND MANUFACTURE METHOD THEREFOR 有权
简体标题：薄膜内存,数组,和其操作方法及制造方法 THIN FILM MEMORY, ARRAY, AND OPERATION METHOD AND MANUFACTURE METHOD THEREFOR
公开(公告)号：TWI264116B
公开(公告)日：2006-10-11
申请号：TW092107778
申请日：2003-04-04
申请人：精工電子有限公司 SEIKO INSTRUMENTS INC. , 林豊 HAYASHI, YUTAKA
发明人：林豊 HAYASHI, YUTAKA , 長谷川尚 , 吉田宜史 , 小山內潤
IPC分类号： H01L
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10802 , H01L27/10844 , Y10S257/908
摘要：一種成形在全空乏SOI或其它半導體薄膜上的記憶胞，在低電壓操作且不需要提供習知記憶胞陣列中的大電容器。半導體薄膜夾於第一與第二半導體區之間，第一與第二半導體區跨過半導體薄膜相互面對且具有第一導電類型。第三半導體區具有相反的導電類型，配置在半導體薄膜的延伸部。來自第三半導體區導電類型相反的載子供應給半導體薄膜部並儲存在其內，以改變由第一導電閘電壓通過絕緣膜在夾於第一與第二半導體區間之半導體薄膜中感生之第一導電類型通道的閘臨限電壓。
简体摘要：一种成形在全空乏SOI或其它半导体薄膜上的记忆胞，在低电压操作且不需要提供习知记忆胞数组中的大电容器。半导体薄膜夹于第一与第二半导体区之间，第一与第二半导体区跨过半导体薄膜相互面对且具有第一导电类型。第三半导体区具有相反的导电类型，配置在半导体薄膜的延伸部。来自第三半导体区导电类型相反的载子供应给半导体薄膜部并存储在其内，以改变由第一导电闸电压通过绝缘膜在夹于第一与第二半导体区间之半导体薄膜中感生之第一导电类型信道的闸临限电压。

2. 发明公开

EP1353386A2 Insulated gate thin film transistor and control system therefor 有权
标题翻译： SteuermethodefürDünnfilmtransistormit isoliertem Gate
公开(公告)号：EP1353386A2
公开(公告)日：2003-10-15
申请号：EP03252252.6
申请日：2003-04-09
申请人： Seiko Instruments Inc. , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi, c/o Seiko Instruments Inc. , Yoshida, Yoshifumi, c/o Seiko Instruments Inc. , Osanai, Jun, c/o Seiko Instruments Inc.
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78615 , H01L21/84 , H01L27/1203
摘要： The gate threshold voltage is electronically controlled in an insulated gate transistor formed in a semiconductor thin film, such as fully depleted SOI, that is depleted of carriers between first and second principal surfaces. A third semiconductor region of the opposite conductivity type is placed such that it is in contact with the semiconductor thin film. The amount of carriers in the semiconductor thin film is controlled by supplying the semiconductor thin film with carriers of the opposite conductivity type from the third semiconductor region, or by drawing carriers of the opposite conductivity type from the semiconductor thin film into the third semiconductor region.
摘要翻译：栅极阈值电压在形成在半导体薄膜（例如完全耗尽的SOI）中的绝缘栅晶体管中被电子控制，其在第一和第二主表面之间耗尽载流子。相反导电型的第三半导体区域被放置成使其与半导体薄膜接触。半导体薄膜中的载流子的量通过向半导体薄膜提供与第三半导体区域相反的导电类型的载流子，或通过将相反导电类型的载流子从半导体薄膜拉入第三半导体区域来控制。

3. 发明授权

EP1355358B1 Thin film semiconductor memory and manufacture method therefor 有权
标题翻译：其制备薄膜半导体存储器和方法
公开(公告)号：EP1355358B1
公开(公告)日：2013-03-13
申请号：EP03252253.4
申请日：2003-04-09
申请人： Seiko Instruments Inc. , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi, c/o Seiko Instruments Inc. , Yoshida, Yoshifumi, c/o Seiko Instruments Inc. , Osanai, Jun, c/o Seiko Instruments Inc.
IPC分类号： H01L27/108 , H01L27/12 , H01L21/84 , H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10802 , H01L27/10844 , Y10S257/908

4. 发明授权

EP1353386B1 Control method for insulated gate thin film transistor 有权
标题翻译：绝缘栅薄膜晶体管的控制方法
公开(公告)号：EP1353386B1
公开(公告)日：2018-02-07
申请号：EP03252252.6
申请日：2003-04-09
申请人： SII Semiconductor Corporation , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi c/o Seiko Instruments Inc. , Yoshida, Yoshifumi c/o Seiko Instruments Inc. , Osanai, Jun c/o Seiko Instruments Inc.
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L29/78615 , H01L21/84 , H01L27/1203
摘要： The gate threshold voltage is electronically controlled in an insulated gate transistor formed in a semiconductor thin film, such as fully depleted SOI, that is depleted of carriers between first and second principal surfaces. A third semiconductor region of the opposite conductivity type is placed such that it is in contact with the semiconductor thin film. The amount of carriers in the semiconductor thin film is controlled by supplying the semiconductor thin film with carriers of the opposite conductivity type from the third semiconductor region, or by drawing carriers of the opposite conductivity type from the semiconductor thin film into the third semiconductor region.

5. 发明公开

EP2113943A3 Thin film memory, array, and operation method and manufacture method therefor 有权
标题翻译：薄膜存储器阵列和操作及其制造方法
公开(公告)号：EP2113943A3
公开(公告)日：2010-10-13
申请号：EP09166746.9
申请日：2003-04-09
申请人： Seiko Instruments Inc. , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi , Yoshida, Yoshifumi , Osanai, Jun
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10802 , H01L27/10844 , Y10S257/908
摘要： A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film (100) is sandwiched between first (110) and second (120) semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region (130) having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate (310) in the semiconductor thin film between the first and second semiconductor regions through an insulating film (210).

6. 发明公开

EP2113943A2 Thin film memory, array, and operation method and manufacture method therefor 有权
标题翻译： Dünnschichtspeicher，Array，und Betriebs- und Herstellungsmethodedafür
公开(公告)号：EP2113943A2
公开(公告)日：2009-11-04
申请号：EP09166746.9
申请日：2003-04-09
申请人： Seiko Instruments Inc. , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi , Yoshida, Yoshifumi , Osanai, Jun
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10802 , H01L27/10844 , Y10S257/908
摘要： A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film (100) is sandwiched between first (110) and second (120) semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region (130) having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate (310) in the semiconductor thin film between the first and second semiconductor regions through an insulating film (210).
摘要翻译：提供了形成在完全耗尽的SOI或其他半导体薄膜上并且在低电压下工作而不需要常规的大电容器的存储单元，以及存储单元阵列。半导体薄膜（100）夹在半导体薄膜之间彼此相对并且具有第一导电类型的第一（110）和第二（120）半导体区域之间。具有相反导电类型的第三半导体区域（130）设置在半导体薄膜的延伸部分中。从第三半导体区域，将相反导电型的载流子提供给并累积在半导体薄膜部分中，以改变由半导体薄层中的第一导电栅极（310）感应的第一导电类型沟道的栅极阈值电压通过绝缘膜（210）在第一和第二半导体区域之间形成膜。

7. 发明公开

EP1353386A3 Insulated gate thin film transistor and control system therefor 有权
标题翻译： Dünnfilmtransistormit isoliertem Gate unddiesbezüglichesKontrollsystem
公开(公告)号：EP1353386A3
公开(公告)日：2004-09-15
申请号：EP03252252.6
申请日：2003-04-09
申请人： Seiko Instruments Inc. , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi, c/o Seiko Instruments Inc. , Yoshida, Yoshifumi, c/o Seiko Instruments Inc. , Osanai, Jun, c/o Seiko Instruments Inc.
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L29/78615 , H01L21/84 , H01L27/1203
摘要： The gate threshold voltage is electronically controlled in an insulated gate transistor formed in a semiconductor thin film, such as fully depleted SOI, that is depleted of carriers between first and second principal surfaces. A third semiconductor region of the opposite conductivity type is placed such that it is in contact with the semiconductor thin film. The amount of carriers in the semiconductor thin film is controlled by supplying the semiconductor thin film with carriers of the opposite conductivity type from the third semiconductor region, or by drawing carriers of the opposite conductivity type from the semiconductor thin film into the third semiconductor region.
摘要翻译：栅极阈值电压在形成于半导体薄膜（例如完全耗尽的SOI）中的绝缘栅极晶体管中被电子控制，其在第一和第二主表面之间耗尽载流子。相反导电型的第三半导体区域被放置成使其与半导体薄膜接触。半导体薄膜中的载流子的量通过向半导体薄膜提供与第三半导体区域相反的导电类型的载流子，或通过将相反导电类型的载流子从半导体薄膜拉入第三半导体区域来控制。

8. 发明公开

EP1355358A3 Thin film semiconductor memory and manufacture method therefor 有权
标题翻译： Dünnfilm-Halbleiterspeicher und Verfahren zur Herstellung desselben
公开(公告)号：EP1355358A3
公开(公告)日：2004-08-04
申请号：EP03252253.4
申请日：2003-04-09
申请人： Seiko Instruments Inc. , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi, c/o Seiko Instruments Inc. , Yoshida, Yoshifumi, c/o Seiko Instruments Inc. , Osanai, Jun, c/o Seiko Instruments Inc.
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10802 , H01L27/10844 , Y10S257/908
摘要： A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film (100) is sandwiched between first (110) and second (120) semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region (130) having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate (310) voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film (210).
摘要翻译：提供了形成在完全耗尽的SOI或其他半导体薄膜上并且在低电压下工作而不需要常规的大电容器的存储单元，以及存储单元阵列。半导体薄膜（100）夹在半导体薄膜之间彼此相对并且具有第一导电类型的第一（110）和第二（120）半导体区域之间。具有相反导电类型的第三半导体区域（130）设置在半导体薄膜的延伸部分中。从第三半导体区域，将相反导电类型的载流子提供给并累积在半导体薄膜部分中，以改变由半导体中的第一导电栅极（310）电压引起的第一导电类型沟道的栅极阈值电压通过绝缘膜（210）在第一和第二半导体区域之间的薄膜。

9. 发明公开

EP1355358A2 Thin film semiconductor memory and manufacture method therefor 有权
标题翻译： Dünnschicht-Halbleiterspeicher und Verfahren zu seiner Herstellung
公开(公告)号：EP1355358A2
公开(公告)日：2003-10-22
申请号：EP03252253.4
申请日：2003-04-09
申请人： Seiko Instruments Inc. , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi, c/o Seiko Instruments Inc. , Yoshida, Yoshifumi, c/o Seiko Instruments Inc. , Osanai, Jun, c/o Seiko Instruments Inc.
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10802 , H01L27/10844 , Y10S257/908
摘要： A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.
摘要翻译：提供了形成在完全耗尽的SOI或其他半导体薄膜上并且在低电压下工作而不需要常规的大电容器的存储单元，以及存储单元阵列。半导体薄膜（100）夹在半导体薄膜之间彼此相对并且具有第一导电类型的第一（110）和第二（120）半导体区域之间。具有相反导电类型的第三半导体区域（130）设置在半导体薄膜的延伸部分中。从第三半导体区域，将相反导电类型的载流子提供给并累积在半导体薄膜部分中，以改变由半导体中的第一导电栅极（310）电压引起的第一导电类型沟道的栅极阈值电压通过绝缘膜（210）在第一和第二半导体区域之间的薄膜。

10. 发明授权

EP2113943B1 Thin film memory, array, and operation method and manufacture method therefor 有权
标题翻译：薄膜存储器阵列和操作及其制造方法
公开(公告)号：EP2113943B1
公开(公告)日：2013-07-31
申请号：EP09166746.9
申请日：2003-04-09
申请人： Seiko Instruments Inc. , Hayashi, Yutaka
发明人： Hayashi, Yutaka , Hasegawa, Hisashi , Yoshida, Yoshifumi , Osanai, Jun
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10802 , H01L27/10844 , Y10S257/908

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