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    • 6. 发明授权
    • Method and structure for low k interlayer dielectric layer
    • 低k层间介质层的方法和结构
    • US07507656B2
    • 2009-03-24
    • US10927828
    • 2004-08-27
    • Guoqing Chen
    • Guoqing Chen
    • H01L21/4763H01L23/522
    • H01L21/7682H01L21/76885H01L2221/1047
    • An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overlying the first interlayer dielectric layer. A contact structure including metallization is within the first interlayer dielectric layer and a metal layer is coupled to the contact structure. A passivation layer is formed overlying the metal layer. Preferably, an air gap layer is coupled between the passivation layer and the metal layer, the air gap layer allowing a portion of the metal layer to be free standing. Depending upon the embodiment, a portion of the air gap layer may be filled with silicon bearing nanoparticles, which may be oxidized at low temperatures. This oxidized layer provides mechanical support and low k dielectric characteristics. Preferably, a portion of the air gap layer is filled with a low k dielectric material as well.
    • 集成电路互连结构。 该结构包括衬底和覆盖衬底的晶体管元件层。 第一层间介质层形成在晶体管元件层上。 形成覆盖在第一层间介电层上的蚀刻停止层。 包括金属化的接触结构在第一层间电介质层内,并且金属层耦合到接触结构。 形成覆盖金属层的钝化层。 优选地,气隙层耦合在钝化层和金属层之间,气隙层允许金属层的一部分自由站立。 根据实施例,气隙层的一部分可以填充有承载硅的纳米颗粒,其可以在低温下被氧化。 该氧化层提供机械支持和低k介电特性。 优选地,气隙层的一部分也用低k电介质材料填充。
    • 8. 发明授权
    • Mask-ROM process and device to prevent punch through using a halo implant process
    • Mask-ROM过程和设备,以防止通过使用光晕植入过程打孔
    • US06940135B2
    • 2005-09-06
    • US10391537
    • 2003-03-17
    • Guoqing ChenRoger Lee
    • Guoqing ChenRoger Lee
    • H01L21/265H01L21/336H01L21/8246H01L27/112H01L29/10
    • H01L29/66583H01L21/26586H01L27/112H01L27/1126H01L29/1045H01L29/66537
    • A method and device for manufacturing a mask ROM integrated circuit device to reduce influences of punch through between source and channel regions that output improper program readings. The method includes forming well regions using an implant process on semiconductor substrate and forming a plurality of buried implant regions through first patterned mask. The first patterned mask is formed overlying the semiconductor substrate. Each of the buried implant regions includes a source region and a drain region for each respective memory cell region. The memory cell region is one of a plurality of memory cell regions. The method also forms pocket regions adjacent to a vicinity of each of the buried implant regions within the channel region for each of the memory cell regions. A first pocket region is defined between the channel region and source region and a second pocket region is defined between the channel region and the drain region for each memory cell region. The method includes programming one or more selected channel regions using implantation to program respective one or more selected memory cell regions.
    • 一种用于制造掩模ROM集成电路器件的方法和装置,用于减少输出不正确程序读数的源极和通道区域之间穿透的影响。 该方法包括使用在半导体衬底上的注入工艺形成阱区,并通过第一图案化掩模形成多个埋置的注入区。 第一图案化掩模形成在半导体衬底上。 每个埋置的注入区域包括用于每个相应存储单元区域的源极区域和漏极区域。 存储单元区域是多个存储单元区域之一。 该方法还形成与每个存储单元区域的通道区域内的每个埋置注入区域附近相邻的凹穴区域。 在沟道区域和源极区域之间限定第一杂质区域,并且在每个存储器单元区域的沟道区域和漏极区域之间限定第二穴状区域。 该方法包括使用植入来编程一个或多个所选择的沟道区域以对相应的一个或多个选择的存储器单元区域进行编程。