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1. 发明授权

US08378082B2 Anti-CD86 antibody 有权
标题翻译：抗CD86抗体
公开(公告)号：US08378082B2
公开(公告)日：2013-02-19
申请号：US12319442
申请日：2009-01-07
申请人： Catherine Aversa Fleener , Robert M. Townsend , Francisco Leon
发明人： Catherine Aversa Fleener , Robert M. Townsend , Francisco Leon
IPC分类号： C07K16/28 , C12N5/12
CPC分类号： C07K16/2827 , G01N33/5047 , G01N33/505 , G01N2333/70532 , G01N2800/245 , Y10S530/809
摘要： The present invention discloses a method for assaying the binding of L104EA29YIg to a receptor. The receptor is preferably CD86 or CD80. The present invention also discloses antibodies to be used in the assay, as well as hybridomas expressing the antibodies.
摘要翻译：本发明公开了一种测定L104EA29YIg与受体结合的方法。受体优选为CD86或CD80。本发明还公开了用于测定中的抗体以及表达抗体的杂交瘤。

2. 发明申请

US20120077207A1 CD86 and CD80 receptor competition assays 有权
标题翻译： CD86和CD80受体竞争测定
公开(公告)号：US20120077207A1
公开(公告)日：2012-03-29
申请号：US12319442
申请日：2009-01-07
申请人： Catherine A. Fleener , Robert M. Townsend , Francisco Leon
发明人： Catherine A. Fleener , Robert M. Townsend , Francisco Leon
IPC分类号： G01N33/566 , C12N5/16 , C07K16/28
CPC分类号： C07K16/2827 , G01N33/5047 , G01N33/505 , G01N2333/70532 , G01N2800/245 , Y10S530/809
摘要： The present invention discloses a method for assaying the binding of L104EA29YIg to a receptor. The receptor is preferably CD86 or CD80. The present invention also discloses antibodies to be used in the assay, as well as hybridomas expressing the antibodies.
摘要翻译：本发明公开了一种测定L104EA29YIg与受体结合的方法。受体优选为CD86或CD80。本发明还公开了用于测定中的抗体以及表达抗体的杂交瘤。

3. 发明申请

US20100167512A1 Methods for Nanostructure Doping 审中-公开
标题翻译：纳米结构掺杂方法
公开(公告)号：US20100167512A1
公开(公告)日：2010-07-01
申请号：US12720125
申请日：2010-03-09
申请人： Yaoling Pan , Jian Chen , Francisco Leon , Shahriar Mostarshed , Linda T. Romano , Vijendra Sahi , David P. Stumbo
发明人： Yaoling Pan , Jian Chen , Francisco Leon , Shahriar Mostarshed , Linda T. Romano , Vijendra Sahi , David P. Stumbo
IPC分类号： H01L21/22
CPC分类号： H01L29/0665 , B81C1/00698 , B81C2201/0173 , B82Y10/00 , H01L21/2256 , H01L21/268 , H01L29/0673
摘要： Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.
摘要翻译：公开了掺杂纳米结构的方法，例如纳米线。该方法提供了改进现有掺杂纳米结构方法的各种方法。这些实施方案包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料以在所得纳米结构内实现新的晶体结构。

4. 发明授权

US07701014B2 Gating configurations and improved contacts in nanowire-based electronic devices 失效
标题翻译：基于纳米线的电子设备的选通配置和改进的接触
公开(公告)号：US07701014B2
公开(公告)日：2010-04-20
申请号：US12244573
申请日：2008-10-02
申请人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
IPC分类号： H01L27/088
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

5. 发明申请

US20090081061A1 PERIPHERALLY PIVOTED OSCILLATING VANE MACHINE 审中-公开
标题翻译：外围摆动振动筛机
公开(公告)号：US20090081061A1
公开(公告)日：2009-03-26
申请号：US12235291
申请日：2008-09-22
申请人： STEPHEN M. CHOMYSZAK , JEDD MARTIN , JAMES T. FERENTINOS , HAI-PING MA , FRANCISCO LEON
发明人： STEPHEN M. CHOMYSZAK , JEDD MARTIN , JAMES T. FERENTINOS , HAI-PING MA , FRANCISCO LEON
IPC分类号： F01C9/00
CPC分类号： F01C9/002 , F01C21/0836
摘要： The present invention is directed to a peripherally pivoted oscillating vane machine (OVM). The OVM has been optimized for performance and efficiency. This has been accomplished by reducing loads on the drive mechanism and by employing de-phased motion of the peripherally pivoted vanes in conjunction with improved porting configurations as well as valve actuation and manufacture.
摘要翻译：本发明涉及一种外围枢转的振荡叶片机（OVM）。 OVM已经针对性能和效率进行了优化。这已经通过减少驱动机构的负载并且通过采用周边枢转叶片的去相位运动以及改进的端口构造以及阀致动和制造而实现。

6. 发明授权

US07345307B2 Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires 失效
标题翻译：用于制造基于导电聚合物和半导体纳米线的塑料电子器件的完全集成的有机分层工艺
公开(公告)号：US07345307B2
公开(公告)日：2008-03-18
申请号：US11233503
申请日：2005-09-22
申请人： Yaoling Pan , Francisco Leon , David P. Stumbo
发明人： Yaoling Pan , Francisco Leon , David P. Stumbo
IPC分类号： H01L29/10
CPC分类号： H01L51/0545 , B82Y10/00 , H01L29/0673 , H01L29/068 , H01L29/78681 , H01L29/7869 , H01L29/78696 , H01L51/0035 , H01L51/0037 , H01L51/0048 , H01L51/0049 , H01L51/0541 , H01L51/0566 , H01L51/4253 , H01L51/4266 , Y02E10/549 , Y02P70/521 , Y10S977/762 , Y10S977/763 , Y10S977/764
摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.
摘要翻译：本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

7. 发明申请

US20080019999A1 Method of vaccinating subjects receiving immune modulating therapy 有权
标题翻译：接种免疫调节疗法接种疫苗的方法
公开(公告)号：US20080019999A1
公开(公告)日：2008-01-24
申请号：US11800860
申请日：2007-05-08
申请人： George Vratsanos , Francisco Leon , Lee Tay , Kenneth Bahrt
发明人： George Vratsanos , Francisco Leon , Lee Tay , Kenneth Bahrt
IPC分类号： A61K39/145 , A61K39/02 , A61P31/16
CPC分类号： C07K14/70521 , A61K39/00 , A61K39/08 , A61K39/092 , A61K39/12 , A61K39/145 , A61K2039/545 , A61K2039/55516 , A61K2039/57 , A61K2039/70 , C07K2319/30 , C07K2319/32 , C12N2760/16134 , C12N2760/16234 , A61K2300/00
摘要： The present invention relates to methods of vaccinating subjects receiving immune modulating therapy, such as soluble CTLA4 molecules, for treatment of immune system diseases mediated by T-cell interactions with B7-positive cells including, but not limited to, autoimmune diseases, immunoproliferative diseases, and immune disorders associated with graft transplantation.
摘要翻译：本发明涉及接种免疫调节治疗的受试者（例如可溶性CTLA4分子）的疫苗接种方法，用于治疗由与B7阳性细胞的T细胞相互作用介导的免疫系统疾病，包括但不限于自身免疫性疾病，免疫增殖性疾病，和与移植物移植相关的免疫疾病。

8. 发明申请

US20070272996A1 Self-aligned implanted waveguide detector 审中-公开
公开(公告)号：US20070272996A1
公开(公告)日：2007-11-29
申请号：US11787187
申请日：2007-04-13
申请人： Francisco Leon , Lawrence West
发明人： Francisco Leon , Lawrence West
IPC分类号： H01L31/075 , H01L31/18
CPC分类号： H01L31/035254 , B82Y20/00 , G02B6/12004
摘要： A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.

9. 发明授权

US08999851B2 Methods for formation of substrate elements 有权
标题翻译：形成基质元素的方法
公开(公告)号：US08999851B2
公开(公告)日：2015-04-07
申请号：US12331150
申请日：2008-12-09
申请人： Francisco Leon , Francesco Lemmi , Jeffrey Miller , David Dutton , David P. Stumbo
发明人： Francisco Leon , Francesco Lemmi , Jeffrey Miller , David Dutton , David P. Stumbo
IPC分类号： H01L21/302 , H01L29/06 , B81C1/00 , B82Y10/00 , H01L29/66 , H01L29/786
CPC分类号： H01L29/0665 , B81C1/00142 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66772 , H01L29/775 , H01L29/78603 , H01L29/78696
摘要： The present invention relates to methods of forming substrate elements, including semiconductor elements such as nanowires, transistors and other structures, as well as the elements formed by such methods.
摘要翻译：本发明涉及形成衬底元件的方法，包括诸如纳米线，晶体管和其它结构的半导体元件，以及由这些方法形成的元件。

10. 发明授权

US07473943B2 Gate configuration for nanowire electronic devices 失效
标题翻译：纳米线电子器件的栅极配置
公开(公告)号：US07473943B2
公开(公告)日：2009-01-06
申请号：US11233398
申请日：2005-09-22
申请人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
发明人： Shahriar Mostarshed , Jian Chen , Francisco Leon , Yaoling Pan , Linda T. Romano
IPC分类号： H01L29/80
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L29/785 , H01L29/78645 , H01L29/78681 , H01L29/7869 , Y10S977/762 , Y10S977/932 , Y10S977/938
摘要： Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
摘要翻译：描述了具有改进的门结构的电子设备的方法，系统和装置。电子装置包括至少一个纳米线。栅极接触沿至少一个纳米线的长度的至少一部分定位。介电材料层在栅极接触和至少一个纳米线之间。源极触点和漏极触点与至少一个纳米线接触。源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。环形第一栅极区域沿着纳米线长度的一部分包围纳米线。第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

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