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    • 3. 发明授权
    • RF clock generator with spurious tone cancellation
    • RF时钟发生器,具有杂音消除
    • US08792581B2
    • 2014-07-29
    • US12708345
    • 2010-02-18
    • Fenghao MuHenrik Sjöland
    • Fenghao MuHenrik Sjöland
    • H03K9/00H04L25/49
    • H03B28/00H03F1/3247
    • A clock generator circuit may generate a target clock signal and may include a pattern generator to generate a pre-distorted version of a modulation signal from patterns stored by the pattern generator. An up-converter may up-convert the pre-distorted version of the modulation signal and a radio frequency lock oscillator signal to obtain an RF clock signal having a desired frequency tone. A tone detection circuit may receive the RF clock signal and detect a presence of unwanted tones. A controller may write the patterns corresponding to the pre-distorted version of the modulation signal to the pattern generator based on the detected unwanted tones in the RF clock signal.
    • 时钟发生器电路可以产生目标时钟信号,并且可以包括模式发生器,以从图案发生器存储的模式产生调制信号的预失真版本。 上变频器可以上变频调制信号的预失真版本和射频锁定振荡器信号,以获得具有期望频率音调的RF时钟信号。 音调检测电路可以接收RF时钟信号并检测不需要的音调的存在。 控制器可以基于RF时钟信号中检测到的不需要的音调将与调制信号的预失真版本对应的模式写入模式发生器。
    • 4. 发明申请
    • Complex Intermediate Frequency Mixer Stage and Calibration Thereof
    • 复杂的中频混频器及其校准
    • US20130183921A1
    • 2013-07-18
    • US13823785
    • 2011-09-16
    • Fenghao MuLars SundströmLeif Wilhelmsson
    • Fenghao MuLars SundströmLeif Wilhelmsson
    • H04B1/06
    • H04B1/06H03D7/166H03D7/18
    • The invention relates to a complex intermediate frequency (CIF) mixer stage, methods of operation thereof, and methods of calibration thereof. The CIF mixer stage comprises numerous individual mixers driven by IF clock signals to down-convert received IF signals into a set of signals at baseband frequency which are further combined to form a lower side band signal and an upper side band signal. The IF clock signals used have a predefined phase relationship among them, which involves tunable phase skews. By calibration of the conversion gains and the phases of the IF clock signals the gain and phase imbalance introduced in a preceding radio frequency mixer stage and/or the CIF mixer stage can be cancelled. Further, in-channel IQ leakage control can be applied to the lower side band signal and/or the upper side band signal. The CIF mixer stage can thus effectively suppress image interference and IQ leakage.
    • 本发明涉及复杂中频(CIF)混频器级,其操作方法及其校准方法。 CIF混频器级包括由IF时钟信号驱动的多个单独的混频器,以将接收到的IF信号降频转换成基带频率的一组信号,这些信号进一步组合以形成下边带信号和上边带信号。 所使用的IF时钟信号之间具有预定的相位关系,这涉及可调节的相位偏差。 通过校准转换增益和IF时钟信号的相位,可以取消在前一个射频混频器级和/或CIF混频器级中引入的增益和相位不平衡。 此外,信道内IQ泄漏控制可以应用于下边带信号和/或上边带信号。 因此,CIF混频器级可以有效地抑制图像干扰和IQ泄漏。
    • 5. 发明授权
    • Passive mixer mismatch tuning using self-tests to suppress IM2
    • 无源混频器不匹配调谐采用自检来抑制IM2
    • US08204467B2
    • 2012-06-19
    • US12368785
    • 2009-02-10
    • Fredrik TillmanFenghao Mu
    • Fredrik TillmanFenghao Mu
    • H04B1/26
    • H04B1/30H03D7/18H03D2200/0086
    • The second-order inter-modulation distortion, originating in a differential passive mixer core from imbalance between devices, is reduced by compensating for the mismatch or load, by means of tuning the differential output impedance at the mixer core, or the input impedance of a filter coupled to the output of the passive mixer. Compensating for the imbalance allows greater suppression of even-order harmonics in the differential structure, which reduces second-order intermodulation at the output of the mixers. The compensation is achieved by tunable resistive elements that are calibrated by a built-in self-test architecture. The calibration circuit is deactivated during receiver operation.
    • 通过调整混频器核心的差分输出阻抗或调制器的输入阻抗,通过补偿失配或负载来减少源自器件之间不平衡的差分无源混频器核心的二阶互调失真 滤波器耦合到无源混频器的输出。 补偿不平衡允许更大的抑制差分结构中的偶次谐波,这减少了混频器输出端的二阶互调。 补偿通过可调电阻元件实现,该电阻元件由内置的自检架构校准。 在接收机操作期间,校准电路被禁用。
    • 6. 发明授权
    • Low power linear interpolation digital-to-analog conversion
    • 低功耗线性插值数模转换
    • US07714759B1
    • 2010-05-11
    • US12254441
    • 2008-10-20
    • Fenghao Mu
    • Fenghao Mu
    • H03M1/78
    • H04L27/206H03M1/661H03M1/785H03M1/808
    • A resistor network digital-to-analog converter (DAC) subdivides each sampling clock cycle of the DAC into a number of phases. For at least one bit input of the DAC associated with a desired input resistor weight, the input bit value is sampled at each phase. Each of those sampled values is then applied to a respective resistor branch, the parallel set of resistor branches forming the parallel equivalent of the desired input resistor weight for that bit input. Such application may be, for example, via a slew-rate controlled driver, to smooth transient edges in the generated analog output signal. The resulting analog signal experiences reduced reconstruction errors at a higher frequency while consuming less power than a comparable oversampling DAC. Shifting reconstruction errors to higher frequencies relaxes downstream filtering requirements, which simplifies analog signal filtering and allows, for example, the use of current-mode low pass filters.
    • 电阻网络数/模转换器(DAC)将DAC的每个采样时钟周期细分为多个阶段。 对于与期望的输入电阻器加权相关联的DAC的至少一个位输入,在每个相位处对输入比特值进行采样。 然后将这些采样值中的每一个施加到相应的电阻器分支,并联的电阻器分支组合形成用于该位输入的期望输入电阻器重量的并行等效值。 这种应用可以是例如经由转换速率控制的驱动器,以平滑所产生的模拟输出信号中的瞬态边沿。 所产生的模拟信号在较高频率下经历减少的重建误差,同时消耗比可比较的过采样DAC更少的功率。 将重建误差转移到较高频率可以放松下游滤波要求,这简化了模拟信号滤波,并允许使用电流模式低通滤波器。
    • 7. 发明申请
    • Method and Apparatus for Tunable Current-Mode Filtering
    • 用于可调谐电流模式滤波的方法和装置
    • US20100066442A1
    • 2010-03-18
    • US12210483
    • 2008-09-15
    • Fenghao Mu
    • Fenghao Mu
    • H03K5/00
    • H03H11/1291
    • According to the teachings presented herein, a tunable current-mode filter is implemented using two or more tunable filter stages in cascade connection. For example, a number of tunable filter stages corresponding to a desired filter order are included in the filter in cascade connection. Use of the current-mode filter simplifies circuit design, particularly in communication transmitter applications, and avoids current-to-voltage conversions needed when voltage-mode filters are used in current-mode signal processing chains. A method and circuit to tune and calibrate the frequency response of the filter are disclosed as well.
    • 根据本文提出的教导,可调谐电流模式滤波器使用级联连接中的两个或多个可调滤波器级来实现。 例如,对应于期望的滤波器顺序的多个可调滤波器级包括在级联中的滤波器中。 电流模式滤波器的使用简化了电路设计,特别是在通信发射机应用中,避免了在电流模式信号处理链中使用电压模式滤波器时所需的电流 - 电压转换。 还公开了调谐和校准滤波器的频率响应的方法和电路。
    • 8. 发明申请
    • Configurable, Variable Gain LNA for Multi-Band RF Receiver
    • 可配置,可变增益LNA多频RF接收机
    • US20080297259A1
    • 2008-12-04
    • US11754696
    • 2007-05-29
    • Fenghao Mu
    • Fenghao Mu
    • H03F3/04
    • H03F1/26H03F1/223H03F1/30H03F1/52H03F1/56H03F3/191H03F3/72H03F2200/111H03F2200/222H03F2200/372H03F2200/429H03F2200/447H03F2200/456H03F2200/489H03F2200/492H03F2203/7206H03F2203/7209H03G1/0088H03G3/3036H03G3/3052
    • A configurable LNA architecture for a multi-band RF receiver front end comprises a bank of LNAs, each optimized to a different frequency band, wherein each LNA has a configurable topology. Each LNA comprises a plurality of amplifier stages, each stage including an RF transistor having a different width. The transistor widths in adjacent amplifier stages may be binary weighted, or may be sized to achieve a constant gain step. By selectively enabling and disabling RF transistors, the effective transistor width of the LNA can be controlled with a fine granularity. A DAC generates a bias voltage with a small quantization step, additionally providing a fine granularity of gain control. The LNAs are protected by overvoltage protection circuits which shield transistors from a supply voltage in excess of their breakdown voltage. A source degeneration inductor presents a real resistance at inputs of the LNAs, without introducing thermal noise.
    • 用于多频带RF接收器前端的可配置LNA架构包括一组LNA,每组优化为不同的频带,其中每个LNA具有可配置的拓扑。 每个LNA包括多个放大器级,每个级包括具有不同宽度的RF晶体管。 相邻放大器级中的晶体管宽度可以是二进制加权的,或者可以被设计成实现恒定的增益步长。 通过选择性地启用和禁用RF晶体管,可以以细粒度控制LNA的有效晶体管宽度。 DAC产生具有小量化步长的偏置电压,另外提供细微的增益控制粒度。 LNA由过电压保护电路保护,该电路将晶体管屏蔽超过其击穿电压的电源电压。 源退化电感器在LNA的输入端呈现实际电阻,而不引入热噪声。
    • 9. 发明授权
    • Transformer filter arrangement
    • 变压器过滤装置
    • US09548155B2
    • 2017-01-17
    • US14233063
    • 2012-07-10
    • Stefan AnderssonFenghao MuJohan Wernehag
    • Stefan AnderssonFenghao MuJohan Wernehag
    • H01F29/02H01F27/42H01F27/34H03H7/01H03H7/09H03H7/38H03H7/42H01F27/28H03H1/00
    • H01F29/02H01F27/2804H01F27/343H01F27/42H03H7/0115H03H7/09H03H7/38H03H7/42H03H7/427H03H2001/0078H03H2007/013
    • A transformer filter arrangement (30) for passing signals at a fundamental frequency and suppressing signals at one or more interfering frequencies is disclosed. It comprises a transformer (100) having a first winding (110) and a second winding (120), wherein the first winding (110) has a first end (112a) and a second end (122b) and the second winding (120) has a first end (122a) and a second end (122b). It further comprises one or more capacitors (130a-e). For each capacitor (130a-c) of a first set of at least one capacitor of the one or more capacitors (130a-e), the capacitor (130a-c) is connected between a pair of taps (a1, a2; b1, b2; c1, c2) of the first winding (110), wherein each tap (a1, a2, b1, b2, c1, c2) of the pair of taps (a1, a2; b1, b2; c1, c2) is located between the first end (112a) and the second end (112b) of the first winding (110), and the capacitor (130a-c), together with an inductive sub segment (140a-c) of the first winding (110), which is connected in parallel with the capacitor (130a-c) between the pair of taps (a1, a2; b1, b2; c1, c2), forms a parallel LC circuit which is tuned to resonate at one of said interfering frequencies for suppressing signals at said one of the interfering frequencies. A corresponding integrated circuit, a corresponding radio receiver circuit, a corresponding radio transmitter circuit, and a corresponding radio communication apparatus are also disclosed.
    • 公开了一种用于以基本频率传递信号并以一个或多个干扰频率抑制信号的变压器滤波器装置(30)。 它包括具有第一绕组(110)和第二绕组(120)的变压器(100),其中第一绕组(110)具有第一端(112a)和第二端(122b)和第二绕组(120) 具有第一端(122a)和第二端(122b)。 它还包括一个或多个电容器(130a-e)。 对于一个或多个电容器(130a-e)中的至少一个电容器的第一组的每个电容器(130a-c),电容器(130a-c)连接在一对抽头(a1,a2; b1, (a1,a2; b1,b2; c1,c2)的每个抽头(a1,a2,b1,b2,c1,c2)位于第一绕组(110)的b2; c1,c2) 在第一绕组(110)的第一端(112a)和第二端(112b)之间,以及电容器(130a-c)与第一绕组(110)的感应子段(140a-c) 其与所述一对抽头(a1,a2; b1,b2; c1,c2)之间的电容器(130a-c)并联连接,形成并联LC电路,其被调谐为以所述干扰频率之一谐振以抑制 在所述一个干扰频率处的信号。 还公开了相应的集成电路,相应的无线电接收器电路,相应的无线电发射机电路和相应的无线电通信装置。