专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060253810A1 Integrated circuit design to optimize manufacturability 审中-公开
标题翻译：集成电路设计，优化可制造性
公开(公告)号：US20060253810A1
公开(公告)日：2006-11-09
申请号：US10572151
申请日：2003-09-16
申请人： Carlo Guardiani , Nicola Dragone , John Kibarian , Enrico Malavasi , Rijko Radocic , Andrzej Strojwas
发明人： Carlo Guardiani , Nicola Dragone , John Kibarian , Enrico Malavasi , Rijko Radocic , Andrzej Strojwas
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： Library design elements (102) are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a library are obtained. Manufacturability attributes (104) of the library design elements are determined for the particular manufacturing process, where manufacturability attributes include yield-related attributes. Library views (106) with manufacturability attributes for the library design elements are then generated, which are utilizing by an electronic design automation (EDA) tool.
摘要翻译：分析库设计元素（102），以便制造可用于设计使用特定制造工艺制造的IC芯片。获取图书馆的图书馆设计元素。确定库设计元素的可制造性属性（104），用于特定制造过程，其中可制造性属性包括屈服相关属性。然后生成具有库设计元素的可制造性属性的库视图（106），其由电子设计自动化（EDA）工具利用。

2. 发明授权

US07487474B2 Designing an integrated circuit to improve yield using a variant design element 失效
标题翻译：设计一个集成电路，以提高产量，使用变体设计元素
公开(公告)号：US07487474B2
公开(公告)日：2009-02-03
申请号：US10541076
申请日：2003-11-17
申请人： Dennis Ciplickas , Joe Davis , Christopher Hess , Sherry Lee , Enrico Malavasi , Abdulmobeen Mohammad , Ratibor Radojcic , Brian Stine , Rakesh Vallishayee , Stefano Zanella , Nicola Dragone , Carlo Guardiani , Michel Quarantelli , Stefano Tonello , Joshi Aniruddha
发明人： Dennis Ciplickas , Joe Davis , Christopher Hess , Sherry Lee , Enrico Malavasi , Abdulmobeen Mohammad , Ratibor Radojcic , Brian Stine , Rakesh Vallishayee , Stefano Zanella , Nicola Dragone , Carlo Guardiani , Michel Quarantelli , Stefano Tonello , Joshi Aniruddha
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.
摘要翻译：集成电路设计用于通过从设计集成电路中使用的一组设计元素获得设计元素来提高制造集成电路时的产量。基于获得的设计元素创建变体设计元素，其中修改所获得的设计元素的特征以创建变体设计元素。确定变体设计元素的产出与面积比。如果变形设计元素的产率与面积之比大于所获得的设计元素的面积比，则变形设计元素被保留以用于设计集成电路。

3. 发明授权

US5663891A Optimization of multiple performance criteria of integrated circuits by expanding a constraint graph with subgraphs derived from multiple PWL convex cost functions 失效
标题翻译：通过从多个PWL凸成本函数导出的子图扩展约束图来优化集成电路的多个性能标准
公开(公告)号：US5663891A
公开(公告)日：1997-09-02
申请号：US627080
申请日：1996-04-03
申请人： Cyrus Bamji , Enrico Malavasi
发明人： Cyrus Bamji , Enrico Malavasi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A system, method, and software product in a computer aided design apparatus for system design, to simultaneously optimize multiple performance criteria models of the system, where the performance criteria models are characterized by convex cost functions based on linear dimensional characteristics of system being designed. One embodiment is provided in a computer aid design environment for integrated circuit design, and used to simultaneously optimize fabrication yield along with other performance criteria. Optimization is provided by converting a structural description of an integrated circuit into a constraint graph, compacting, and modifying the constraint graph to include convex cost functions for selected performance criteria to optimized, such as yield cost functions. The cost functions are then transformed to piecewise linear cost functions. The constraint graph is then expanded by replacing edges having piecewise linear cost function with subgraphs constructed from the piecewise linear cost function. The expanded constraint graph is then minimized using a network flow algorithm. Once minimized, the constraint graph describes the positions of circuit elements that maximize yield (and other selected performance criteria) given the cost functions.
摘要翻译：一种用于系统设计的计算机辅助设计装置中的系统，方法和软件产品，同时优化系统的多个性能标准模型，其中性能标准模型以基于正在设计的系统的线性尺寸特征的凸成本函数为特征。在用于集成电路设计的计算机辅助设计环境中提供了一个实施例，并且用于同时优化制造产量以及其他性能标准。通过将集成电路的结构描述转换为约束图，压缩和修改约束图以包括用于优化的所选性能标准的凸成本函数（例如收益成本函数）来提供优化。然后将成本函数转换为分段线性成本函数。然后通过用分段线性成本函数构造的子图替换具有分段线性成本函数的边来扩展约束图。然后使用网络流算法将扩展约束图最小化。一旦最小化，约束图描述了考虑成本函数最大化产量（和其他所选性能标准）的电路元件的位置。

4. 发明申请

US20060101355A1 Yield improvement 失效
标题翻译：产量提高
公开(公告)号：US20060101355A1
公开(公告)日：2006-05-11
申请号：US10541076
申请日：2003-11-17
申请人： Dennis Ciplickas , Joe Davis , Christopher Hess , Sherry Lee , Enrico Malavasi , Abdulmobeen Mohammad , Ratibor Radojcic , Brian Stine , Rakesh Vallishayee , Stefano Zanella , Nicola Dragone , Carlo Guardiani , Michel Quarantelli , Stefano Tonello , Joshi Aniruddha
发明人： Dennis Ciplickas , Joe Davis , Christopher Hess , Sherry Lee , Enrico Malavasi , Abdulmobeen Mohammad , Ratibor Radojcic , Brian Stine , Rakesh Vallishayee , Stefano Zanella , Nicola Dragone , Carlo Guardiani , Michel Quarantelli , Stefano Tonello , Joshi Aniruddha
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit
摘要翻译：集成电路设计用于通过从设计集成电路中使用的一组设计元素获得设计元素来提高制造集成电路时的产量。基于获得的设计元素创建变体设计元素，其中修改所获得的设计元素的特征以创建变体设计元素。确定变体设计元素的产出与面积比。如果变形设计元件的屈服面积比大于获得的设计元素的屈服面积比，则变形设计元素被保留用于设计集成电路

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式