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1. 发明授权

US08981478B2 Recessed source and drain regions for FinFETs 有权
标题翻译：嵌入式FinFET的源极和漏极区域
公开(公告)号：US08981478B2
公开(公告)日：2015-03-17
申请号：US13611335
申请日：2012-09-12
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.
摘要翻译：半导体器件和方法包括通过在半导体层上限定翅片硬掩模来形成鳍状场效应晶体管，在散热片硬掩模上形成虚拟结构，以在半导体层上建立平面区域，去除超出鳍片硬掩模的一部分蚀刻与虚拟结构相邻的半导体层，以产生凹陷的源极和漏极区域，去除虚设结构，蚀刻平面区域中的半导体层以产生鳍片，以及在鳍片上形成栅极叠层。

2. 发明授权

US08936972B2 Epitaxially thickened doped or undoped core nanowire FET structure and method for increasing effective device width 有权
标题翻译：外延增厚的掺杂或未掺杂的核心纳米线FET结构和增加有效器件宽度的方法
公开(公告)号：US08936972B2
公开(公告)日：2015-01-20
申请号：US13596234
申请日：2012-08-28
申请人： Sarunya Bangsaruntip , Guy Cohen , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/84 , H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02428 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.
摘要翻译：提供了增加纳米线FET器件的有效器件宽度的技术。一方面，提供一种制造FET器件的方法。该方法包括以下步骤。提供了在BOX上具有SOI层的SOI晶片，其中SOI层存在于掩埋氮化物层和氮化物盖之间。蚀刻SOI层，埋入氮化物层和氮化物盖，以形成阶梯状构造的SOI层中的纳米线芯和焊盘。纳米线芯悬挂在BOX上。外延侧壁形成在纳米线芯的侧壁上。从纳米线芯中去除掩埋氮化物层和氮化物盖。形成围绕纳米线芯和外延侧壁中的每一个的至少一部分的栅叠层。

3. 发明授权

US08816327B2 Nanowire efuses 有权
标题翻译：纳米线efuses
公开(公告)号：US08816327B2
公开(公告)日：2014-08-26
申请号：US13611081
申请日：2012-09-12
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L29/78 , H01L23/525
CPC分类号： H01L29/785 , H01H2085/0283 , H01H2300/036 , H01L23/5256 , H01L29/0673 , H01L29/42392 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses and methods for forming the same are shown that include forming a wire between a first pad and a second pad on a substrate, forming a blocking structure around a portion of the wire, and depositing a metal layer on the wire and first and second pads to form a metal compound, wherein the metal compound fully penetrates the portion of the wire within the blocking structure.
摘要翻译：示出了电可编程熔丝及其形成方法，其包括在基板上的第一焊盘和第二焊盘之间形成导线，在焊丝的一部分周围形成阻挡结构，以及在焊丝上沉积金属层，第二垫以形成金属化合物，其中所述金属化合物完全穿透所述阻挡结构内的所述金属丝的所述部分。

4. 发明授权

US08669615B1 Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices 有权
标题翻译：金属门功能工程技术可实现多个阈值电压FINFET器件
公开(公告)号：US08669615B1
公开(公告)日：2014-03-11
申请号：US13611257
申请日：2012-09-12
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a FIN FET device is provided. The FIN FET device includes a SOI wafer having an oxide layer and a SOI layer over a BOX, and a plurality of fins patterned in the oxide layer and the SOI layer; an interfacial oxide on the fins; and at least one gate stack on the interfacial oxide, the gate stack having (i) a conformal gate dielectric layer present, (ii) a conformal gate metal layer, and (iii) a conformal work function setting material layer. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer present in the gate stack is proportional to a pitch of the fins.
摘要翻译：在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。在一个方面，提供一种FIN FET器件。 FIN FET器件包括在BOX上具有氧化物层和SOI层的SOI晶片和在氧化物层和SOI层中图案化的多个鳍状物; 翅片上的界面氧化物; 和界面氧化物上的至少一个栅极堆叠，所述栅极堆叠具有（i）存在共形栅极电介质层，（ii）共形栅极金属层，和（iii）共形功函数设定材料层。存在于栅极堆叠中的共形栅极金属层的体积和共形功函数设定材料层的体积与散热片的间距成正比。

5. 发明授权

US08597991B2 Embedded silicon germanium n-type filed effect transistor for reduced floating body effect 有权
公开(公告)号：US08597991B2
公开(公告)日：2013-12-03
申请号：US13568689
申请日：2012-08-07
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/8238 , H01L29/66636 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A method for fabricating a semiconductor device includes forming a gate stack on an active region of a silicon-on-insulator substrate. The active region is within a semiconductor layer and is doped with an p-type dopant. A gate spacer is formed surrounding the gate stack. A first trench is formed in a region reserved for a source region and a second trench is formed in a region reserved for a drain region. The first and second trenches are formed while maintaining exposed the region reserved for the source region and the region reserved for the drain region. Silicon germanium is epitaxially grown within the first trench and the second trench while maintaining exposed the regions reserved for the source and drain regions, respectively.

6. 发明授权

US08526228B2 8-transistor SRAM cell design with outer pass-gate diodes 有权
标题翻译：具有外部通过栅极二极管的8晶体管SRAM单元设计
公开(公告)号：US08526228B2
公开(公告)日：2013-09-03
申请号：US13345636
申请日：2012-01-06
申请人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： G11C11/36 , G11C16/24
CPC分类号： G11C16/24 , G11C11/412 , H01L27/0207 , H01L27/1104 , H01L27/1116
摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.
摘要翻译：一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置中的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

7. 发明申请

US20130214357A1 NON-PLANAR MOSFET STRUCTURES WITH ASYMMETRIC RECESSED SOURCE DRAINS AND METHODS FOR MAKING THE SAME 有权
标题翻译：具有不对称吸收源排水的非平面MOSFET结构及其制造方法
公开(公告)号：US20130214357A1
公开(公告)日：2013-08-22
申请号：US13398339
申请日：2012-02-16
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/0657 , H01L29/66795
摘要： Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.
摘要翻译：非平面金属氧化物场效应晶体管（MOSFET）和用于制造具有改进的外在电阻和边缘电容的具有不对称，凹陷源极和漏极的非平面MOSFET的方法。这些方法包括最后一个替代栅极工艺，以形成非平面MOSFET并且采用逆向金属剥离工艺来形成不对称的源极/漏极凹槽。剥离过程产生一个从门结构偏离的凹槽，而第二凹槽与结构对准。因此，源/漏不对称性通过源极/漏极的物理结构实现，而不仅仅是通过离子注入来实现。所得到的非平面器件具有接触漏极侧的基本上未掺杂的区域和源极侧的掺杂区域的翅片的第一通道，因此第一通道是不对称的。鳍的顶表面上的通道是对称的，因为它接触漏极和源极侧上的掺杂区域。

8. 发明申请

US20130161744A1 FINFET WITH MERGED FINS AND VERTICAL SILICIDE 有权
标题翻译：具有合并的FINS和垂直硅胶的FINFET
公开(公告)号：US20130161744A1
公开(公告)日：2013-06-27
申请号：US13337874
申请日：2011-12-27
申请人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
发明人： Veeraraghavan S. BASKER , Andres Bryant , Huiming Bu , Wilfried Haensch , Effendi Leobandung , Chung-Hsun Lin , Theodorus E. Standaert , Tenko Yamashita , Chun-chen Yeh
IPC分类号： H01L27/12 , H01L29/78 , H01L21/336
CPC分类号： H01L29/41791 , H01L29/66795
摘要： A finFET device is provided. The finFET device includes a BOX layer, fin structures located over the BOX layer, a gate stack located over the fin structures, gate spacers located on vertical sidewalls of the gate stack, an epi layer covering the fin structures, source and drain regions located in the semiconductor layers of the fin structures, and silicide regions abutting the source and drain regions. The fin structures each comprise a semiconductor layer and extend in a first direction, and the gate stack extends in a second direction that is perpendicular. The gate stack comprises a high-K dielectric layer and a metal gate, and the epi layer merges the fin structures together. The silicide regions each include a vertical portion located on the vertical sidewall of the source or drain region.
摘要翻译：提供了finFET器件。 finFET器件包括BOX层，位于BOX层上方的翅片结构，位于鳍结构上方的栅极堆叠，位于栅叠层的垂直侧壁上的栅极隔离物，覆盖翅片结构的外延层，位于翅片结构的半导体层和邻接源极和漏极区域的硅化物区域。翅片结构各自包括半导体层并沿第一方向延伸，并且栅极堆叠沿垂直的第二方向延伸。栅极堆叠包括高K电介质层和金属栅极，并且外延层将鳍结构融合在一起。硅化物区域各自包括位于源极或漏极区域的垂直侧壁上的垂直部分。

9. 发明申请

US20130153997A1 HYBRID CMOS NANOWIRE MESH DEVICE AND BULK CMOS DEVICE 有权
公开(公告)号：US20130153997A1
公开(公告)日：2013-06-20
申请号：US13328106
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/088 , H01L21/28 , H01L29/78 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/66545 , B82Y10/00 , B82Y40/00 , H01L27/088 , H01L27/1207 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66553 , H01L29/66651 , H01L29/66795 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a bulk CMOS device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the bulk CMOS device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和体CMOS器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和体CMOS器件的半导体结构。

10. 发明申请

US20130153993A1 HYBRID CMOS NANOWIRE MESH DEVICE AND FINFET DEVICE 有权
标题翻译： HYBRID CMOS NANOWIRE MESH器件和FINFET器件
公开(公告)号：US20130153993A1
公开(公告)日：2013-06-20
申请号：US13328015
申请日：2011-12-16
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/28 , B82Y99/00 , B82Y40/00
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L29/78696
摘要： A method of forming a hybrid semiconductor structure on an SOI substrate. The method includes an integrated process flow to form a nanowire mesh device and a FINFET device on the same SOI substrate. Also included is a semiconductor structure which includes the nanowire mesh device and the FINFET device on the same SOI substrate.
摘要翻译：一种在SOI衬底上形成混合半导体结构的方法。该方法包括在同一SOI衬底上形成纳米线网状器件和FINFET器件的集成工艺流程。还包括在同一SOI衬底上包括纳米线网状器件和FINFET器件的半导体结构。

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