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1. 发明授权

US08202766B2 Method for fabricating through-silicon via structure 有权
标题翻译：通硅结构制造方法
公开(公告)号：US08202766B2
公开(公告)日：2012-06-19
申请号：US12487665
申请日：2009-06-19
申请人： Chien-Li Kuo
发明人： Chien-Li Kuo
IPC分类号： H01L21/768 , H01L21/56
CPC分类号： H01L21/76898
摘要： A method for fabricating through-silicon via structure includes the steps of: providing a semiconductor substrate; forming at least one semiconductor device on surface of the semiconductor substrate; forming a dielectric layer on the semiconductor device, in which the dielectric layer includes at least one via hole; forming a first conductive layer on the dielectric layer and filling the via hole; performing an etching process to form a through-silicon via in the first conductive layer, the dielectric layer, and the semiconductor substrate; depositing a second conductive layer in the through-silicon via and partially on the first conductive layer; and planarizing a portion of the second conductive layer until reaching the surface of the first conductive layer.
摘要翻译：一种用于制造穿硅通孔结构的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底的表面上形成至少一个半导体器件; 在所述半导体器件上形成电介质层，其中所述电介质层包括至少一个通孔; 在所述电介质层上形成第一导电层并填充所述通孔; 在所述第一导电层，所述电介质层和所述半导体衬底中进行蚀刻工艺以形成贯通硅通孔; 在所述穿硅通孔中并部分地在所述第一导电层上沉积第二导电层; 以及平坦化所述第二导电层的一部分直到到达所述第一导电层的表面。

2. 发明申请

US20120112782A1 METHOD FOR PREDICTING TOLERABLE SPACING BETWEEN CONDUCTORS IN SEMICONDUCTOR PROCESS 有权
标题翻译：用于预测半导体工艺中导体之间容差的方法
公开(公告)号：US20120112782A1
公开(公告)日：2012-05-10
申请号：US12941652
申请日：2010-11-08
申请人： Chien-Li Kuo , Wen-Jung Liao , Jiun-Hau Liao , Min-Chin Hsieh , Chun-Liang Hou , Shuen-Cheng Lei
发明人： Chien-Li Kuo , Wen-Jung Liao , Jiun-Hau Liao , Min-Chin Hsieh , Chun-Liang Hou , Shuen-Cheng Lei
IPC分类号： G01R31/26
CPC分类号： G01R31/2644
摘要： A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Δd to d−Δd wherein d is the standard spacing and Δd
摘要翻译：提供了一种用于预测可接受的对门间距的方法。首先，提供具有多个源极/漏极触点的晶片。然后，通过使用光掩模在晶片上形成多条测试栅极线。在一个模具中，从d +＆Dgr; d到d-＆Dgr; d的不同的接触到栅极距离，其中d是标准间距和＆Dgr; d

3. 发明授权

US08168533B2 Through-silicon via structure and method for making the same 有权
标题翻译：通硅结构及其制作方法
公开(公告)号：US08168533B2
公开(公告)日：2012-05-01
申请号：US13215246
申请日：2011-08-23
申请人： Chien-Li Kuo
发明人： Chien-Li Kuo
IPC分类号： H01L23/538
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/13 , H01L2224/0554 , H01L2224/05573 , H01L2224/056 , H01L2224/13009 , H01L2224/13025 , H01L2924/00014 , H01L2924/1461 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.
摘要翻译：贯通硅通孔结构包括具有第一侧和第二侧的衬底，连接第一侧和第二侧的通孔，并填充有导电材料，钝化层设置在第一侧和覆盖层上所述贯通硅孔和保护环围绕但不与所述贯通硅孔接触并被所述第一面和所述第二面露出。保护环填充绝缘材料。

4. 发明申请

US20110300708A1 THROUGH-SILICON VIA STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译：通过硅的结构和方法制造它们
公开(公告)号：US20110300708A1
公开(公告)日：2011-12-08
申请号：US13215246
申请日：2011-08-23
申请人： Chien-Li Kuo
发明人： Chien-Li Kuo
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/13 , H01L2224/0554 , H01L2224/05573 , H01L2224/056 , H01L2224/13009 , H01L2224/13025 , H01L2924/00014 , H01L2924/1461 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.
摘要翻译：贯通硅通孔结构包括具有第一侧和第二侧的衬底，连接第一侧和第二侧的通孔，并填充有导电材料，钝化层设置在第一侧上并与其接触所述贯通硅孔和保护环围绕但不与所述贯通硅孔接触并被所述第一面和所述第二面露出。保护环填充绝缘材料。

5. 发明授权

US08026573B2 Electrical fuse structure 有权
标题翻译：电熔丝结构
公开(公告)号：US08026573B2
公开(公告)日：2011-09-27
申请号：US12335510
申请日：2008-12-15
申请人： Chien-Li Kuo , Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin
发明人： Chien-Li Kuo , Yung-Chang Lin , Kuei-Sheng Wu , San-Fu Lin
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse structure is disclosed. The electrical fuse structure includes a fuse element disposed on surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse element, and an anode electrically connected to another end of the fuse element. Specifically, a compressive stress layer is disposed on at least a portion of the fuse element.
摘要翻译：公开了电熔丝结构。电熔丝结构包括设置在半导体衬底的表面上的熔丝元件，与熔丝元件的一端电连接的阴极以及与熔丝元件的另一端电连接的阳极。具体而言，压电应力层设置在熔丝元件的至少一部分上。

6. 发明申请

US20100224965A1 THROUGH-SILICON VIA STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：通过硅的结构和方法制造它们
公开(公告)号：US20100224965A1
公开(公告)日：2010-09-09
申请号：US12399987
申请日：2009-03-09
申请人： Chien-Li Kuo
发明人： Chien-Li Kuo
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/13 , H01L2224/0554 , H01L2224/05573 , H01L2224/056 , H01L2224/13009 , H01L2224/13025 , H01L2924/00014 , H01L2924/1461 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.
摘要翻译：贯通硅通孔结构包括具有第一侧和第二侧的衬底，连接第一侧和第二侧的通孔，并填充有导电材料，钝化层设置在第一侧上并与其接触所述贯通硅孔和保护环围绕但不与所述贯通硅孔接触并被所述第一面和所述第二面露出。保护环填充绝缘材料。

7. 发明授权

US07588991B2 Method for fabricating embedded static random access memory 有权
标题翻译：嵌入式静态随机存取存储器的制作方法
公开(公告)号：US07588991B2
公开(公告)日：2009-09-15
申请号：US11779880
申请日：2007-07-18
申请人： Tung-Hsing Lee , Chien-Li Kuo , Yun-San Huang , Chih-Ming Su , Buo-Chin Hsu
发明人： Tung-Hsing Lee , Chien-Li Kuo , Yun-San Huang , Chih-Ming Su , Buo-Chin Hsu
IPC分类号： H01L21/331
CPC分类号： H01L27/1104 , H01L27/105 , H01L27/1116
摘要： The present invention provides a method for fabricating an embedded static random access memory, including providing a semiconductor substrate; defining a logic area and a memory cell area on the semiconductor substrate and defining at least a first conductive device area and at least a second conductive device area in the logic area and the memory cell area respectively; forming a patterned mask on the memory cell area and on the second conductive device area in the logic area and exposing the first conductive device area in the logic area; performing a first conductive ion implantation process on the exposed first conductive device area in the logic area; and removing the patterned mask.
摘要翻译：本发明提供了一种制造嵌入式静态随机存取存储器的方法，包括提供半导体衬底; 在所述半导体衬底上限定逻辑区域和存储单元区域，并分别在所述逻辑区域和所述存储器单元区域中至少限定第一导电器件区域和至少第二导电器件区域; 在所述存储单元区域和所述逻辑区域中的所述第二导电器件区域上形成图案化掩模，并且暴露所述逻辑区域中的所述第一导电器件区域; 在所述逻辑区域中暴露的第一导电器件区域上执行第一导电离子注入工艺; 并去除图案化掩模。

8. 发明申请

US20080220341A1 MASK PATTERN AND METHOD FOR FORMING THE SAME 有权
标题翻译：掩模图案及其形成方法
公开(公告)号：US20080220341A1
公开(公告)日：2008-09-11
申请号：US11683778
申请日：2007-03-08
申请人： Chuan-Hsien Fu , Chuen-Huei Yang , Chien-Li Kuo , Shu-Ru Wang , Yu-Lin Wang
发明人： Chuan-Hsien Fu , Chuen-Huei Yang , Chien-Li Kuo , Shu-Ru Wang , Yu-Lin Wang
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening.
摘要翻译：本发明提供一种掩模图案。掩模图案至少包括连续图案。每个连续图案具有第一图案，第二图案和一组辅助图案。辅助图案位于第一图案与第二图案之间。第一种图案，辅助图案和第二图案一起形成封闭的开口。

9. 发明授权

US07256475B2 On-chip test circuit for assessing chip integrity 有权
标题翻译：用于评估芯片完整性的片上测试电路
公开(公告)号：US07256475B2
公开(公告)日：2007-08-14
申请号：US11161304
申请日：2005-07-29
申请人： Jui-Meng Jao , Chien-Li Kuo
发明人： Jui-Meng Jao , Chien-Li Kuo
IPC分类号： H01L23/00
CPC分类号： G01R31/2884 , G01R31/2853 , H01L23/562 , H01L23/585 , H01L2224/05001 , H01L2224/05085 , H01L2224/05568 , H01L2224/13 , H01L2924/00014 , H01L2224/05599
摘要： A semiconductor chip includes an active inner circuit; a die seal ring surrounding the active inner circuit; a first circuit structure fabricated at a first corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the first circuit structure has a first solder pad; and a second circuit structure fabricated at a second corner of the semiconductor chip outside the die seal ring and electrically connected to the die seal, wherein the second circuit structure has a second solder pad.
摘要翻译：半导体芯片包括有源内部电路; 围绕有源内部电路的模具密封环; 第一电路结构，其制造在所述半导体芯片的位于所述模具密封环外部的第一角部并电连接到所述模具密封件，其中所述第一电路结构具有第一焊盘; 以及第二电路结构，其在所述半导体芯片的位于所述模具密封环的外部的第二角处制造并电连接到所述模具密封件，其中所述第二电路结构具有第二焊盘。

10. 发明授权

US07250670B2 Semiconductor structure and fabricating method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US07250670B2
公开(公告)日：2007-07-31
申请号：US11162863
申请日：2005-09-27
申请人： Chien-Li Kuo , Bing-Chang Wu , Jui-Meng Jao
发明人： Chien-Li Kuo , Bing-Chang Wu , Jui-Meng Jao
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L23/5283 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.
摘要翻译：提供半导体结构。半导体结构设置在晶片的划线上并且在晶片的芯片区域周围。半导体结构包括顺序地设置在划线上的多个电介质层和设置在每个电介质层中的多个金属图案。设置在每个电介质层中的金属图案延伸到下一个下面的介电层。

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