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1. 发明专利

JP2005217804A Image processing apparatus 审中-公开
标题翻译：图像处理设备
公开(公告)号：JP2005217804A
公开(公告)日：2005-08-11
申请号：JP2004022317
申请日：2004-01-30
申请人： Atsushi Iwata , 穆岩田
发明人： KAMEDA SEIJI , IWATA ATSUSHI , SASAKI MAMORU , YOSHIKAWA KIMIMARO
IPC分类号： G06T1/20 , H04N5/225 , H04N5/335 , H04N5/372 , H04N5/374
摘要： PROBLEM TO BE SOLVED: To solve the problem where the wiring between chips becomes complex by adopting the radio connection technique between chips in an image processing apparatus utilizing a multichip system. SOLUTION: An image acquisition chip 22 and a plurality of image processing chips 23 are arranged in a hierarchy. A photosensor and a processing circuit are arranged at each pixel in the image acquisition chip 22, and a pixel memory and a processing circuit are arranged at each pixel in the image processing chip 23. Chips arranged in a hierarchy are connected by radio while rows are in parallel by local connection 25. Image information acquired by the image acquisition chip 22 can be subjected to speedy and highly functional image processing in an ultra-parallel and hierarchical structure. Further, an adaptation control chip 24 and the processing chips 22, 23 in a hierarchy are connected by global connection 26, thus controlling the plurality of processing chips 22, 23 arranged in a hierarchy by radio connection in adaptation according to a visual environment. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了解决利用多芯片系统的图像处理装置中的芯片之间采用无线连接技术，芯片之间的布线变得复杂的问题。解决方案：图像采集芯片22和多个图像处理芯片23被分层布置。在图像采集芯片22中的每个像素处布置有光电传感器和处理电路，并且在图像处理芯片23中的每个像素处布置有像素存储器和处理电路。层级布置的芯片通过无线电连接，而行是通过本地连接25并行。图像获取芯片22获取的图像信息可以以超平行和分层结构进行快速和高功能的图像处理。此外，通过全局连接26连接适应控制芯片24和处理芯片22,23，从而通过根据视觉环境的适应性的无线连接来控制分层布置的多个处理芯片22,23。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005203657A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2005203657A
公开(公告)日：2005-07-28
申请号：JP2004010053
申请日：2004-01-19
申请人： Atsushi Iwata , 穆岩田
发明人： SASAKI MAMORU , IWATA ATSUSHI , ARIZONO DAISUKE
IPC分类号： H01L25/18 , H01L21/822 , H01L25/065 , H01L25/07 , H01L27/04
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of saving a formation of an inter-chip connection electrode having a complex step in a three dimensional integration and requiring no accurate inter-chip positioning owing to a wireless connection, capable of suppressing a transmission power by using a resonance characteristic to realize a lowered power consumption of a communication circuit, further capable of decreasing an area of a plane inductor to realize a multichannel, and capable of easily radiating heat of an internal chip by widening a chip interval.
SOLUTION: The wireless signal transfer for wiring connection between chips is realized by the electromagnetic coupling between plane inductors formed on a laminated IC chips instead of an electrode for the connection between chips. The resonance circuit is realized on the IC chip by forming a capacity together with the plane inductor. The digital transmission producing no bit error at high speed in the wireless communication between chips is realized by equalizing the transmission frequency to the resonance frequency, and by further suppressing an unnecessary residual vibration causing an intersymbol interference.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供能够在三维集成中节省具有复杂步骤的芯片间连接电极的形成的半导体器件，并且由于无线连接而不需要准确的芯片间定位，能够通过使用谐振特性来抑制发送功率以实现通信电路的降低的功耗，还能够减小平面电感器的面积以实现多通道，并且能够通过加宽芯片间隔来容易地散热内部芯片的热量。解决方案：通过形成在层叠IC芯片上的平面电感器之间的电磁耦合而不是用于芯片之间的连接的电极来实现芯片之间的布线连接的无线信号传输。通过与平面电感器一起形成容量，在IC芯片上实现谐振电路。通过将发送频率与谐振频率进行均衡，并且进一步抑制引起码间干扰的不必要的残留振动，实现芯片之间的无线通信中高速无错误的数字传输。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2004201026A Programmable analog/digital converter 有权
公开(公告)号：JP2004201026A
公开(公告)日：2004-07-15
申请号：JP2002367136
申请日：2002-12-18
申请人： Interface:Kk , Atsushi Iwata , Japan Science & Technology Agency , 穆岩田 , 株式会社インタフェース , 独立行政法人科学技術振興機構
发明人： YAMAGUCHI KEIJI , IWATA ATSUSHI , MORI HIROKI , KABEMOTO NAOKI , NISHIDA TADASHI
IPC分类号： H03M1/12 , H03M1/38 , H03M1/42
摘要： PROBLEM TO BE SOLVED: To provide a programmable analog/digital converter which can vary resolution and conversion speed by a control signal from outside. SOLUTION: A plurality of analog signal input channels 101 and a sample and hold (S/H) circuit 102 are connected by a first switch group 110. The S/H circuit 102 and a comparator 103 are connected by a second switch group 120. A switch control part 40 controls operations of the first and second switch groups 110 and 120 in accordance with an operation mode setting signal 8 from the outside. Thus, analog signals by the number of the input channels are sampled and held at variable conversion speeds. Sampled and held values are converted into digital values of the number of variable bits by a sequential conversion system. The number of the input channels, conversion speed and resolution can flexibly be varied. COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP2004178021A Digital information processing circuit 有权
标题翻译：数字信息处理电路
公开(公告)号：JP2004178021A
公开(公告)日：2004-06-24
申请号：JP2002340091
申请日：2002-11-22
申请人： Hiroshima Industrial Promotion Organization , Atsushi Iwata , 穆岩田 , 財団法人ひろしま産業振興機構
发明人： MORIE TAKASHI , ANDO HIROSHI , IWATA ATSUSHI , ISHIZU TAKAAKI
IPC分类号： G06T1/20 , G06N3/063
摘要： PROBLEM TO BE SOLVED: To provide a digital information processing circuit capable of mounting a relaxation type image processing circuit and the like in the form of a digital circuit with less circuit scale.
SOLUTION: When a control signal CLK is High, a voltage difference (Ii-Oi) is calculated. Subsequently, a difference between data, which are N-bit data, of REG1 and that of REG2 is calculated, while a code is outputted from a sign terminal, and an absolute value of the difference is passed through a decoder to be converted into N' bit data to be inputted into an LUT1. An output of the LUT1 is K-bit (K
摘要翻译：要解决的问题：提供一种数字信息处理电路，其能够以较小电路规模的数字电路的形式安装松弛型图像处理电路等。解决方案：当控制信号CLK为高电平时，计算电压差（Ii-Oi）。随后，计算REG1的数据和REG2的数据之间的差异，同时从符号终端输出代码，并将差分的绝对值通过解码器转换为N '位数据输入到LUT1中。 LUT1的输出是K位（K

5. 发明专利

JP2004104384A Orthogonal conversion circuit of image 审中-公开
公开(公告)号：JP2004104384A
公开(公告)日：2004-04-02
申请号：JP2002262316
申请日：2002-09-09
申请人： Atsushi Iwata , 岩田穆
发明人： IWATA ATSUSHI , KATAYAMA MITSUSUKE , MORIE TAKASHI
IPC分类号： G06F17/14 , H03M7/30 , H04N19/436 , H04N19/60 , H04N19/85 , H04N7/30
摘要： PROBLEM TO BE SOLVED: To provide a circuit in which an orthogonal conversion coefficient is operated accurately and at a high speed to a high-resolution two-dimensional image by operations with pixel juxtaposition, by using an analog circuit with improved calculation accuracy.
SOLUTION: The circuit has an operating means to multiply a two-dimensional image orthogonal conversion matrix by each pixel value of the two-dimensional image by generating the two-dimensional image orthogonal conversion matrix from the one-dimensional basis function, and a means to operate an orthogonal conversion coefficient to the high-resolution two-dimensional image by adding currents to the multiplied results with a voltage-stabilized common line.
COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2003044850A Method and device for extracting image area 审中-公开
标题翻译：提取图像区域的方法和装置
公开(公告)号：JP2003044850A
公开(公告)日：2003-02-14
申请号：JP2001232964
申请日：2001-07-31
申请人： Atsushi Iwata , Takashi Morie , 穆岩田 , 隆森江
发明人： MORIE TAKASHI , NAKANO TEPPEI , IWATA ATSUSHI , NAGATA MAKOTO
IPC分类号： G06T1/20 , G06T7/00
摘要： PROBLEM TO BE SOLVED: To make an area extraction function easily includable in a circuit for acquiring area boundary information in pixel parallel processing by providing a method for sequentially and fast extracting closed areas defined on the basis of area boundary pixel information at temporally different timing and a device composed of a circuit for performing the method.
SOLUTION: Image edge pixels and area boundary pixels are set in a first state with respect to an image with an area boundary given, pixels other than the image edge pixels and area boundary pixels are set in a second state, one optional pixel in the second state is next set in a third state, if any among adjacent pixels is in the third state with respect to the whole pixels in the second state, processing that changes the pixel to be in the third state is repeated, the position information of the pixel in the third state is outputted when pixels to be changed do not exist any more, the pixel in the third state is subsequently made to be in the first state, and these series of processing are repeated until the pixels in the second state do not exist any more.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：通过提供一种在时间上不同的定时提供基于区域边界像素信息定义的闭合区域的方法，通过提供用于获取像素并行处理中的区域边界信息的电路中容易地包括区域提取功能，以及由用于执行该方法的电路组成的装置。解决方案：图像边缘像素和区域边界像素相对于给定面积边界的图像被设置在第一状态中，除了图像边缘像素和区域边界像素之外的像素被设置在第二状态，第二状态中的一个可选像素下一个状态被设置在第三状态中，如果相邻像素中的任一个相对于第二状态下的整个像素处于第三状态，则重复改变为处于第三状态的像素的处理，则像素的位置信息在不再存在要改变的像素的情况下输出第三状态，随后使第三状态的像素处于第一状态，并且重复这些系列处理，直到不存在第二状态的像素再说了

7. 发明专利

JP2002368116A Method and apparatus for analyzing potential of integrated circuit board 有权
标题翻译：用于分析集成电路板电位的方法和装置
公开(公告)号：JP2002368116A
公开(公告)日：2002-12-20
申请号：JP2001177830
申请日：2001-06-12
申请人： Atsushi Iwata , 穆岩田
发明人： IWATA ATSUSHI , MURASAKA YOSHITAKA , NAGATA MAKOTO
IPC分类号： G01R31/28 , G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04 , H01L29/00
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a substrate model which enables potential variation analysis of an integrated circuit substrate for large-scale integrated circuits and an analyzing method and apparatus, using the same.
SOLUTION: The semiconductor integrated circuit substrate is modeled with resistance meshes, a low-resistance ground wiring having substrate contacts is connected to the substrate and it is divided into regions bounded with ground wiring portions. A plurality of resistance meshes obtained after division form a substrate equivalent circuit, composed of only resistances between their respective analysis nodes. Connection nodes between them are provided, in the horizontal direction on the ground wiring and located, in the vertical direction between the boundaries one by one, and they are connected to form an equivalent circuit model of the substrate to analyze.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种形成能够对大规模集成电路的集成电路基板进行电位变化分析的基板模型的方法和使用其的分析方法和装置。解决方案：半导体集成电路基板用电阻网格建模，具有基板触点的低电阻接地布线连接到基板，并被划分为与接地布线部分有界的区域。分割后获得的多个电阻网格构成基板等效电路，其仅由它们各自的分析节点之间的电阻构成。它们之间的连接节点在地线上的水平方向上被提供，并且沿着垂直方向在边界之间逐个地被提供，并且它们被连接以形成衬底的等效电路模型以进行分析。

8. 发明专利

JP2004145493A Matching arithmetic circuit 审中-公开
公开(公告)号：JP2004145493A
公开(公告)日：2004-05-20
申请号：JP2002307739
申请日：2002-10-23
申请人： Hiroshima Industrial Promotion Organization , Atsushi Iwata , 岩田穆 , 財団法人ひろしま産業振興機構
发明人： IWATA ATSUSHI , YAMAMOTO YOSHIKO , TAKEDA MIKIO , WATABE YUKI , MORIE TAKASHI , WATANABE MUTSUMI , SAKATA AKIHISA
IPC分类号： G06F15/16 , G06T1/20 , G06T1/60 , G06T7/00
摘要： PROBLEM TO BE SOLVED: To provide a matching arithmetic circuit capable of dividing and holding an image, and carrying out the matching arithmetic operation of a plurality of standard data in parallel at high speed, and changing a retrieval range.
SOLUTION: A standard image and a reference image are divided by a number being the power of 2, respectively, and a memory is divided by the number of lines larger than the half of the maximum number of lines of a matching block so that address control among divided memories and access control can be simplified. Also, points whose similarity is high are selected from among similarity arithmetic results calculated in the plurality of divided reference image areas so that a matching arithmetic operation in a retrieval range across the plurality of divided images can be carried out.
COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2004145476A Matching arithmetic circuit 审中-公开
公开(公告)号：JP2004145476A
公开(公告)日：2004-05-20
申请号：JP2002307479
申请日：2002-10-22
申请人： Hiroshima Industrial Promotion Organization , Atsushi Iwata , 岩田穆 , 財団法人ひろしま産業振興機構
发明人： IWATA ATSUSHI , YAMAMOTO YOSHIKO , TAKEDA MIKIO , WATABE YUKI , MORIE TAKASHI , WATANABE MUTSUMI , SAKATA AKIHISA
IPC分类号： G06T1/60 , G06T7/00
摘要： PROBLEM TO BE SOLVED: To provide a matching arithmetic circuit capable of quickly calculating the similarity of multiple reference data of certain standard data in parallel.
SOLUTION: Data are stored in a memory so that each line of a reference image memory can be folded so that the reading data width can be reduced, and that multiple reference data necessary for a parallel matching operation can be simultaneously read. Furthermore, the reading result is stored in a shift register, and data for one line of the reference data are applied to a PE which calculates similarity by a shift arithmetic operation, and the number of times of access to the memory is reduced, and a stand-by time necessary for reading the data is reduced so that the overall processing time can be quickened.
COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2004145473A Matching arithmetic circuit 审中-公开
公开(公告)号：JP2004145473A
公开(公告)日：2004-05-20
申请号：JP2002307455
申请日：2002-10-22
申请人： Hiroshima Industrial Promotion Organization , Atsushi Iwata , 岩田穆 , 財団法人ひろしま産業振興機構
发明人： IWATA ATSUSHI , YAMAMOTO YOSHIKO , TAKEDA MIKIO , WATABE YUKI , MORIE TAKASHI , WATANABE MUTSUMI , SAKATA AKIHISA
IPC分类号： G06T7/00
摘要： PROBLEM TO BE SOLVED: To provide a matching arithmetic circuit capable of efficiently carrying out processing by selecting pixels for carrying out a matching arithmetic operation, and selecting arithmetic contents in those pixels since an image principally includes points whose matching is impossible or points whose correct matching positions are difficult to calculate.
SOLUTION: This matching arithmetic circuit is provided with a flag memory for storing the processing contents of respective pixels (the selection of processing to be executed, corresponding point retrieval range, matching block size), and the value is read for each pixel, and the processing contents are selected so that a matching arithmetic operation can be executed.
COPYRIGHT: (C)2004,JPO

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