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1. 发明专利

JP2015534287A 半導体デバイス及びその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2015534287A
公开(公告)日：2015-11-26
申请号：JP2015541911
申请日：2013-11-08
申请人：アムコアテクノロジーインコーポレイテッドAmkor Technology, Inc. , アムコアテクノロジーインコーポレイテッドAmkor Technology, Inc.
发明人：ウォンチュルド , ウォンチュルド , ドゥヒュンパク , ドゥヒュンパク , チョンシクペク , チョンシクペク , ジフンイ , ジフンイ , ソンミンソ , ソンミンソ
IPC分类号： H01L23/12 , H01L23/28 , H01L23/32 , H01L23/40
CPC分类号： H01L21/4846 , H01L21/481 , H01L21/4853 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L23/04 , H01L23/3128 , H01L23/3135 , H01L23/3675 , H01L23/49811 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0655 , H01L2221/68345 , H01L2221/68381 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/81191 , H01L2224/814 , H01L2224/81801 , H01L2224/83005 , H01L2224/92125 , H01L2924/05042 , H01L2924/05442 , H01L2924/10253 , H01L2924/15311 , H01L2924/16251 , H01L2924/1816 , H01L2924/18161 , H01L2924/19105 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要：貫通シリコンビアがなく比較的薄いインターポーザを含む半導体デバイス及びその製造方法を提供する。半導体デバイスの製造方法において、再分配層と誘電体層とを備えるインターポーザをダミー基板上に形成し、半導体ダイをインターポーザの上部に対向する再分配層に接続し、封入材を用いて半導体ダイを封入し、インターポーザからダミー基板を除去し、バンプをインターポーザの下部に対向する再分配層に接続する。
摘要翻译：提供一种半导体装置及方法，其包括相对薄的内插器没有TSV的制造方法。制造半导体器件的方法中，以形成内插器和一个再分布层和虚设基板上的介电层，以及连接到面向上的内插器的顶部上的半导体管芯的再分布层，半导体用封装材料死包封的，和从所述插入件的伪基片被连接到设置在插入器的底部面向所述凸块的重分布层。

2. 发明专利

DE69911320D1 未知
公开(公告)号：DE69911320D1
公开(公告)日：2003-10-23
申请号：DE69911320
申请日：1999-07-07
申请人： AMKOR TECHNOLOGY INC , AMKOR TECHNOLOGY INC , NAT STARCH CHEM INVEST
发明人： KWAK JAE-SUNG , MOON BYUNG-HOON
IPC分类号： C08L63/00 , H01L21/52 , C09J163/00 , C09J201/00 , H01L23/28 , H01L23/495
摘要： Disclosed is an adhesive resin composition for bonding semiconductor chips comprising an adhesive resin component, a curing agent, a diluent, a curing promoter, a thixotropic agent, and an inorganic filler component. The resin component is approximately 10-50% by weight, and the inorganic filler component is approximately 50-90% by weight and comprises a copper ingredient and a silver ingredient. The copper ingredient is selected from the group consisting of CuO, Cu2O, with the mixtures thereof being approximately 0.1-50% by weight based on the total weight of said inorganic filler component. The silver ingredient is approximately 50-99.0% by weight based on the total weight of the inorganic filler ingredient.

3. 发明公开

KR20180006839A 클립 정렬 노치를 갖는 반도체 패키지 및 관련 방법 审中-公开
标题翻译：半导体封装与夹式排列切口及相关方法
公开(公告)号：KR20180006839A
公开(公告)日：2018-01-19
申请号：KR20170036855
申请日：2017-03-23
申请人： AMKOR TECHNOLOGY INC
发明人： MANGRUM MARC ALAN
IPC分类号： H01L23/40 , H01L23/00 , H01L23/495
CPC分类号： H01L23/49575 , H01L23/49513 , H01L23/49517 , H01L23/49524 , H01L23/49548 , H01L23/49562 , H01L23/49565 , H01L24/69 , H01L2224/69
摘要： 일실시예에서, 전자부품은리드프레임및 제1반도체다이를포함할 수있다. 리드프레임은리드프레임상면, 리드프레임상면과반대인리드프레임하면, 및리드프레임상면에서의상부노치를포함할 수있다. 상부노치는리드프레임상면과리드프레임하면사이에위치되고, 상부노치의노치길이를정의하는상부노치베이스를포함할 수있고, 노치길이를따라, 리드프레임상면으로부터상부노치베이스까지연장된상부노치제1측벽을또한포함할수 있다. 제1반도체다이는다이상면, 다이상면과반대이며리드프레임상면상으로탑재된다이하면, 그리고다이주변부를포함할수 있다. 상부노치는다이주변부외부에위치될수 있다. 다른예들및 관련방법이본 명세서에개시되어있다.
摘要翻译：电子组件包括引线框架和第一半导体管芯。引线框包括引线框顶侧，与引线框顶侧相对的引线框底侧，以及引线框顶侧的顶部凹口。顶切口包括位于引线框顶侧和引线框底侧之间并限定顶切口的切口长度的顶切口底座，并且还可包括沿着切口长度从引线框顶部延伸的顶切口第一侧壁一边到顶尖基地。第一半导体管芯可以包括管芯顶侧，与管芯顶侧相对的管芯底侧以及安装到引线框顶侧和管芯周边。顶尖可位于模具周边之外。本文还公开了其他示例和相关方法。

4. 发明专利

MY121395A EPOXY RESIN COMPOSITION FOR BONDING SEMICONDUCTOR CHIPS 未知
公开(公告)号：MY121395A
公开(公告)日：2006-01-28
申请号：MYPI9902847
申请日：1999-07-07
申请人： AMKOR TECHNOLOGY INC , AMKOR TECHNOLOGY INC , NAT STRACH AND CHEMICAL INVEST HOLDING CORP
发明人： KWAK JAE-SUNG , MOON BYUNG-HOON
IPC分类号： C08K3/08 , C08L63/00 , H01L21/52 , C08L63/02 , C09J163/00 , C09J201/00 , H01L23/28 , H01L23/495
摘要： DISCLOSED IS AN ADHESIVE RESIN COMPOSITION FOR BONDING SEMICONDUCTOR CHIPS COMPRISING AN ADHENSIVE RESIN COMPONENT, A CURING AGENT, A DILUENT, A CURINMG PROMOTER, A THIXOTROPIC AGENT, AND AN INORGANIC FILLER COMPONENT. THE RESIN COMPONENT IS APPROXIMATELY 10-50BY WEIGHT, AND THE INORGANIC FILLER COMPONENT IS APPROXIMTELY 50-90BY WEIGHT AND COMPRISES A COPPER INGREDIENT AND A SILVER INGREDIENT. THE COPPER INGREDIENT IS SELECTED FROM THE GROUP CONSISTING OF CUO, CU2O, WITH THE MIXTURES THEREOF BEING APPROXIMATELY 0.1-50BY WEIGHT BASED ON THE TOTAL WEIGHT OF SAID INORGANIC FILLER COMPONENT. THE SILVER INGREDIENT IS APPROXIMATELY 50-99.0BY WEIGHT BASED ON THE TOTAL WEIGHT OF THE INORGANIC FILLER INGREDIENT.

5. 发明专利

PT971009E 未知
公开(公告)号：PT971009E
公开(公告)日：2004-02-27
申请号：PT99113152
申请日：1999-07-07
申请人： AMKOR TECHNOLOGY INC , AMKOR TECHNOLOGY INC , NAT STARCH AND CHE INV HOLDING
发明人： KWAK JAE-SUNG , MOON BYUNG-HOON
IPC分类号： C08L63/00 , H01L21/52 , C09J163/00 , C09J201/00 , H01L23/28 , H01L23/495
摘要： Disclosed is an adhesive resin composition for bonding semiconductor chips comprising an adhesive resin component, a curing agent, a diluent, a curing promoter, a thixotropic agent, and an inorganic filler component. The resin component is approximately 10-50% by weight, and the inorganic filler component is approximately 50-90% by weight and comprises a copper ingredient and a silver ingredient. The copper ingredient is selected from the group consisting of CuO, Cu2O, with the mixtures thereof being approximately 0.1-50% by weight based on the total weight of said inorganic filler component. The silver ingredient is approximately 50-99.0% by weight based on the total weight of the inorganic filler ingredient.

6. 发明专利

DE69911320T2 未知
公开(公告)号：DE69911320T2
公开(公告)日：2004-07-08
申请号：DE69911320
申请日：1999-07-07
申请人： AMKOR TECHNOLOGY INC , AMKOR TECHNOLOGY INC , NAT STARCH CHEM INVEST
发明人： KWAK JAE-SUNG , MOON BYUNG-HOON
IPC分类号： C08L63/00 , H01L21/52 , C09J163/00 , C09J201/00 , H01L23/28 , H01L23/495
摘要： Disclosed is an adhesive resin composition for bonding semiconductor chips comprising an adhesive resin component, a curing agent, a diluent, a curing promoter, a thixotropic agent, and an inorganic filler component. The resin component is approximately 10-50% by weight, and the inorganic filler component is approximately 50-90% by weight and comprises a copper ingredient and a silver ingredient. The copper ingredient is selected from the group consisting of CuO, Cu2O, with the mixtures thereof being approximately 0.1-50% by weight based on the total weight of said inorganic filler component. The silver ingredient is approximately 50-99.0% by weight based on the total weight of the inorganic filler ingredient.

7. 发明公开

KR20180054397A 반도체 디바이스 및 그의 제조 방법 审中-公开
公开(公告)号：KR20180054397A
公开(公告)日：2018-05-24
申请号：KR20170005570
申请日：2017-01-12
申请人： AMKOR TECHNOLOGY INC
发明人： HAMES GREG , RINNE GLENN , BALARAMAN DEVARAJAN
IPC分类号： H01L21/768
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/11462 , H01L2224/11614 , H01L2224/13026
摘要： 반도체디바이스및 반도체디바이스의제조방법을제공한다. 비제한적인예들로서, 본발명의다양한양태들은측방향도금공정을적어도부분적으로수행함으로써상호연결구조들을형성하는단계를포함하는반도체디바이스를제조하는방법, 및그에의해제조된반도체디바이스를제공한다.

8. 发明授权

KR101111430B1 Mold for manufacturing semiconductor package and Method for molding semiconductor package using the same 有权
标题翻译：用于制造半导体封装的模具和使用其的半导体封装的模制方法
公开(公告)号：KR101111430B1
公开(公告)日：2012-02-15
申请号：KR20100073895
申请日：2010-07-30
申请人： AMKOR TECHNOLOGY INC
发明人： KIM JAE YUN , GIM IN HO , KWON SOON DONG
IPC分类号： H01L23/28 , H01L23/02
CPC分类号： H01L2224/16 , H01L2924/15311
摘要： PURPOSE: A mold for manufacturing a semiconductor package and a method for molding a semiconductor package are provided to prevent a void between a semiconductor chip and a printed circuit board by separately controlling the speed or volume of molding compound resin which is discharged from each gate to a molding area. CONSTITUTION: An air vent hole(30) is formed in the outlet of a cavity. A plurality of gates are connected to the cavity in a mold and are formed with a constant space. The cavity is filled with molding compound resin(16) via gates. A first gate(28a) corresponds to the center of a flip chip connection space between a semiconductor chip and a substrate. A second gate and a third gate are located on either side of the first gate and correspond to a frame of the flip chip connection space. A fourth gate(28d) and a fifth gate(28e) correspond to a peripheral area of the semiconductor chip exiting the flip chip connection space.
摘要翻译：目的：提供一种用于制造半导体封装的模具和用于模制半导体封装的方法，以通过分别控制从每个栅极排出的模塑复合树脂的速度或体积来防止半导体芯片和印刷电路板之间的空隙一个成型区域。构成：在空腔的出口形成通气孔（30）。多个门连接到模具中的腔体并形成有恒定的空间。模腔通过浇口填充模塑复合树脂（16）。第一栅极（28a）对应于半导体芯片和衬底之间的倒装芯片连接空间的中心。第二栅极和第三栅极位于第一栅极的任一侧，并且对应于倒装芯片连接空间的框架。第四栅极（28d）和第五栅极（28e）对应于离开倒装芯片连接空间的半导体芯片的周边区域。

9. 发明公开

KR20100025218A Semiconductor device and fabricating method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：KR20100025218A
公开(公告)日：2010-03-09
申请号：KR20080083903
申请日：2008-08-27
申请人： AMKOR TECHNOLOGY INC
发明人： KIM JAE YOON , PARK CHAN YOK , JUNG YOON HA
IPC分类号： H01L23/34
CPC分类号： H01L24/73 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2924/00012
摘要： PURPOSE: A semiconductor device and a method for manufacturing the same are provided to reduce the generation of noise signal by maintaining conductive wires with a constant length. CONSTITUTION: A substrate(110) includes an insulation layer(111), a land(112) which is exposed to the lower surface of the insulation layer and a redistribution layer(113). One end of the redistribution layer is electrically connected to the land through the insulating layer. The other end of the redistribution layer is routed along the upper side of the insulating layer. A semiconductor die(120) is attached on the upper side of the substrate. A conductive wire(130) electrically connected to the redistribution layer and the semiconductor die. An encapsulant(140) is formed on the upper side of the substrate to cover the semiconductor die.
摘要翻译：目的：提供半导体器件及其制造方法，以通过保持具有恒定长度的导线来减少噪声信号的产生。构成：衬底（110）包括绝缘层（111），暴露于绝缘层的下表面的焊盘（112）和再分布层（113）。再分配层的一端通过绝缘层电连接到焊盘。再分配层的另一端沿着绝缘层的上侧布线。半导体管芯（120）安装在基板的上侧。电连接到再分配层和半导体管芯的导线（130）。密封剂（140）形成在衬底的上侧以覆盖半导体管芯。

10. 发明公开

KR20150093632A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：KR20150093632A
公开(公告)日：2015-08-18
申请号：KR20150105773
申请日：2015-07-27
申请人： AMKOR TECHNOLOGY INC
发明人： PARK DOO HYUN , SEO SEONG MIN , PAEK JONG SIK , DO WON CHUL , LEE WANG GU
IPC分类号： H01L23/58 , H01L21/283 , H01L23/495
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： 본 발명의 일 실시예는 반도체 디바이스 및 그 제조 방법에 관한 것으로, 해결하고자 하는 기술적 과제는 도금 방식을 통하여 반도체 다이와 회로기판, 또는 반도체 다이와 반도체 다이를 전기적으로 연결함으로써, 일렉트로 마이그레이션(electromigration) 현상을 제거하고, 이에 따라 접속 계면의 접속 신뢰성을 향상시킬 수 있는 반도체 디바이스 및 그 제조 방법을 제공하는데 있다.
이를 위해 본 발명은 도전성 패턴을 포함하는 서브스트레이트; 도전성 필러를 포함하며, 상기 도전성 필러가 상기 도전성 패턴에 전기적으로 접속된 반도체 다이; 및, 상기 도전성 패턴 및 도전성 필러를 전기적으로 접속하는 도금층을 포함함하는 반도체 디바이스를 개시한다.
摘要翻译：本发明的实施例涉及半导体器件及其制造方法。要解决的技术目的是提供一种半导体器件，其通过电镀方法电连接半导体管芯和半导体管芯或半导体管芯和电路板，从而去除电迁移并提高接触界面的接触可靠性，以及制造方法。为此，半导体器件包括：包括导电图案的衬底; 半导体管芯，其包括电连接到所述导电图案的导电填料; 以及将导电图案和导电填料电连接的镀层。

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