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    • 6. 发明申请
    • COMMUNICATION PROCESSOR AND COMMUNICATION PROCESSING METHOD
    • 通信处理器和通信处理方法
    • US20130223265A1
    • 2013-08-29
    • US13881292
    • 2011-10-26
    • Hidekuni YomoKiyotaka KobayashiAkihiko MatsuokaAtsushi Maruyama
    • Hidekuni YomoKiyotaka KobayashiAkihiko MatsuokaAtsushi Maruyama
    • H04W72/04
    • H04W72/0446H04B1/0003H04B1/406H04W88/06
    • The present invention provides a communication processor that is compatible with a plurality of communication protocols and also limits increases in circuit scale. A communication processor (200) comprises a computational processing circuit resource (270) having a plurality of programmable computation units (FU: Function Unit). An operation mode determination unit (230) determines an operation mode indicating a communication protocol application state. A permitted processing time determination unit (240) determines a permitted processing time in accordance with the determined operation mode. A resource allocation unit (250), in accordance with the permitted processing time, divides the plurality of FUs and allocates computational resources for each communication protocol indicated by the operation mode. A region controller (260) controls the allocated computation resources. The computational processing circuit resource (270) outputs data from after the computational processing at the timing when the computation processing ends.
    • 本发明提供了一种与多种通信协议兼容的通信处理器,并且还限制了电路规模的增加。 通信处理器(200)包括具有多个可编程计算单元(FU:功能单元)的计算处理电路资源(270)。 操作模式确定单元(230)确定指示通信协议应用状态的操作模式。 允许处理时间确定单元(240)根据确定的操作模式确定允许的处理时间。 资源分配单元(250)根据允许的处理时间对多个FU进行分割,并为由操作模式指示的每个通信协议分配计算资源。 区域控制器(260)控制所分配的计算资源。 计算处理电路资源(270)在计算处理结束的定时从计算处理之后输出数据。
    • 9. 发明授权
    • Fast Fourier transformation circuit
    • 快速傅里叶变换电路
    • US08145694B2
    • 2012-03-27
    • US12094966
    • 2006-11-16
    • Kentaro MiyanoKatsuaki AbeAkihiko Matsuoka
    • Kentaro MiyanoKatsuaki AbeAkihiko Matsuoka
    • G06F17/14
    • G06F17/142H04L27/265
    • Provided is a fast Fourier transformation circuit capable of optimizing an operation resource while matching a plurality of communication systems. In this circuit, an FFT circuit (100) comprises a first FFT operation unit (110) for subjecting two-parallel 2 digital signals to FFT operations of (M−1) steps, a second FFT operation unit (120) for subjecting 2 digital signals to FFT operations of (N−M+1) steps, and a third FFT operation unit (130) for subjecting 2 digital signals to an FFT operation of one step. The output signal of the first FFT operation unit (110) is subjected to the FFT operation by the second FFT operation unit (120) and the third FFT operation unit (130) thereby to perform the FFT operations of 2 points and 2 points simultaneously.
    • 提供了一种能够在匹配多个通信系统的同时优化操作资源的快速傅里叶变换电路。 在该电路中,FFT电路(100)包括用于对(M-1)步的FFT运算进行二并联2 数字信号的第一FFT运算单元(110),第二FFT运算单元 (N-M + 1)个步骤的FFT操作的第二FFT运算单元(130),用于对2个数字信号进行一步的FFT运算。 第一FFT运算单元(110)的输出信号由第二FFT运算单元(120)和第三FFT运算单元(130)进行FFT运算,从而进行2点的FFT运算,2 同时点。