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1. 发明授权

US07729192B2 Circuit and method for reducing power in a memory device during standby modes 失效
标题翻译：用于在待机模式下降低存储器件功耗的电路和方法
公开(公告)号：US07729192B2
公开(公告)日：2010-06-01
申请号：US12325736
申请日：2008-12-01
申请人： Aaron M. Schoenfeld
发明人： Aaron M. Schoenfeld
IPC分类号： G11C5/14
CPC分类号： G11C11/40615 , G11C5/14 , G11C7/1045 , G11C11/406 , G11C11/4074 , G11C2207/2227 , G11C2211/4067
摘要： A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs for further reducing the power to portions of the memory device.
摘要翻译：公开了一种响应于待机模式命令以减少存储器件内部操作功率的存储器件。存储器件包括用于在待机模式期间降低功率的电路，其中电路包括具有至少第一和第二参考信号的参考。该电路还包括用于响应于待机模式命令在第一和第二参考信号之间切换的开关装置，并进一步控制内部操作功率调节器以在正常和低功率输出之间进行调节，以进一步降低存储器部分的功率设备。

2. 发明申请

US20100014371A1 CIRCUIT AND METHOD FOR CONTROLLING A CLOCK SYNCHRONIZING CIRCUIT FOR LOW POWER REFRESH OPERATION 有权
标题翻译：用于控制低功耗刷新电路的时钟同步电路的电路和方法
公开(公告)号：US20100014371A1
公开(公告)日：2010-01-21
申请号：US12568507
申请日：2009-09-28
申请人： Aaron M. Schoenfeld , Ross E. Dermott
发明人： Aaron M. Schoenfeld , Ross E. Dermott
IPC分类号： G11C7/00 , G11C8/18 , G11C8/00
CPC分类号： G11C7/222 , G11C7/22 , G11C11/406 , G11C2211/4061 , G11C2211/4067
摘要： A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.
摘要翻译：提供一种方法和装置，用于在执行存储器件中的刷新操作期间的至少一部分时间内使时钟同步电路空转。在接收外部时钟信号的存储器件中，提供一种用于执行刷新操作的方法和装置，其包括启动存储器件中的至少一个刷新操作，并停止产生相对于外部时钟信号定时的内部时钟信号对于至少一次刷新操作需要完成的时间的至少一部分。

3. 发明授权

US07257884B2 Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or input/output configuration 有权
标题翻译：用于制造具有用于电气特性或输入/输出配置的调节电路的半导体部件的方法
公开(公告)号：US07257884B2
公开(公告)日：2007-08-21
申请号：US11210562
申请日：2005-08-24
申请人： Aaron M. Schoenfeld , David J. Corisis , Tyler J. Gomm
发明人： Aaron M. Schoenfeld , David J. Corisis , Tyler J. Gomm
IPC分类号： H01H69/02
CPC分类号： H01L24/06 , H01L23/3128 , H01L23/49838 , H01L23/5382 , H01L23/66 , H01L24/48 , H01L24/97 , H01L2224/04042 , H01L2224/05553 , H01L2224/05599 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05669 , H01L2224/05678 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/06136 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/85424 , H01L2224/85444 , H01L2224/85455 , H01L2224/8547 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , Y10T29/49002 , Y10T29/49004 , Y10T29/49105 , Y10T29/49107 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49156 , Y10T29/49162 , Y10T29/49222 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.
摘要翻译：半导体部件包括调整电路，其被配置为调整部件或其元件的选定的物理和电特性以及该部件的输入/输出配置。该组件包括半导体管芯，附着到管芯的衬底以及衬底上的端子触点。调节电路包括与管芯和端子触点电连通的导体和可编程链路，例如熔丝或反熔丝。调节电路还可以包括电容器和电感导体。使用激光或编程信号，可编程链路可以被置于选定的状态（例如，短路或开路）。一种用于制造组件的方法包括以下步骤：形成调整电路，然后将可编程链路放置在所选择的状态以实现所选择的调整。

4. 发明授权

US07208935B2 Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer 有权
公开(公告)号：US07208935B2
公开(公告)日：2007-04-24
申请号：US10366922
申请日：2003-02-13
申请人： Mark T. Van Horn , Richard N. Hedden , David R. Cuthbert , Aaron M. Schoenfeld
发明人： Mark T. Van Horn , Richard N. Hedden , David R. Cuthbert , Aaron M. Schoenfeld
IPC分类号： G01R31/02 , G01R27/04
CPC分类号： G01R31/04 , G01R1/0408 , G01R1/06772 , G01R27/2617 , G01R31/2896 , H01L24/73 , H01L2224/32013 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48253 , H01L2224/4847 , H01L2224/73265 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

5. 发明授权

US07155630B2 Method and unit for selectively enabling an input buffer based on an indication of a clock transition 有权
标题翻译：用于基于时钟转换的指示选择性地使能输入缓冲器的方法和单元
公开(公告)号：US07155630B2
公开(公告)日：2006-12-26
申请号：US10179445
申请日：2002-06-25
申请人： Debra M. Bell , Aaron M. Schoenfeld
发明人： Debra M. Bell , Aaron M. Schoenfeld
IPC分类号： G06F1/04 , G06F1/32
CPC分类号： G06F1/12
摘要： A system unit including a processor unit and an input storage unit. The processor unit generates an input signal and a clock signal. The input storage unit receives the input signal and the clock signal. The input storage unit processes the clock signal to generate an input buffer enable signal. The input buffer enable signal changes from an inactive state to an active state a short time interval before at least one of the transitions of the clock signal. A method includes receiving a clock signal having a plurality of transitions at an input buffer unit, enabling the input buffer unit before each of the plurality of transitions, and disabling the input buffer unit after each of the plurality of transitions.
摘要翻译：一种系统单元，包括处理器单元和输入存储单元。处理器单元产生输入信号和时钟信号。输入存储单元接收输入信号和时钟信号。输入存储单元处理时钟信号以产生输入缓冲器使能信号。输入缓冲器使能信号在时钟信号的至少一个转换之前的短时间间隔内从非活动状态变为有效状态。一种方法包括在输入缓冲器单元处接收具有多个转换的时钟信号，使得能够在多个转换中的每一个之前输入缓冲器单元，并且在多个转换中的每一个之后禁用输入缓冲器单元。

6. 发明授权

US07106646B2 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation 有权
公开(公告)号：US07106646B2
公开(公告)日：2006-09-12
申请号：US11184187
申请日：2005-07-18
申请人： Aaron M. Schoenfeld , Ross E. Dermott
发明人： Aaron M. Schoenfeld , Ross E. Dermott
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C7/22 , G11C11/406 , G11C2211/4061 , G11C2211/4067
摘要： A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.

7. 发明授权

US07007375B2 Method for fabricating a semiconductor component 失效
标题翻译：半导体部件的制造方法
公开(公告)号：US07007375B2
公开(公告)日：2006-03-07
申请号：US10403741
申请日：2003-03-31
申请人： Aaron M. Schoenfeld , David J. Corisis , Tyler J. Gomm
发明人： Aaron M. Schoenfeld , David J. Corisis , Tyler J. Gomm
IPC分类号： H01H69/02
CPC分类号： H01L24/06 , H01L23/3128 , H01L23/49838 , H01L23/5382 , H01L23/66 , H01L24/48 , H01L24/97 , H01L2224/04042 , H01L2224/05553 , H01L2224/05599 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05669 , H01L2224/05678 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/06136 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/85424 , H01L2224/85444 , H01L2224/85455 , H01L2224/8547 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , Y10T29/49002 , Y10T29/49004 , Y10T29/49105 , Y10T29/49107 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49156 , Y10T29/49162 , Y10T29/49222 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.
摘要翻译：半导体部件包括调整电路，其被配置为调整部件或其元件的选定的物理和电特性以及该部件的输入/输出配置。该组件包括半导体管芯，附着到管芯的衬底以及衬底上的端子触点。调节电路包括与管芯和端子触点电连通的导体和可编程链路，例如熔丝或反熔丝。调节电路还可以包括电容器和电感导体。使用激光或编程信号，可编程链路可以被置于选定的状态（例如，短路或开路）。一种用于制造组件的方法包括以下步骤：形成调整电路，然后将可编程链路放置在所选择的状态以实现所选择的调整。

8. 发明授权

US06903994B1 Device, system and method for reducing power in a memory device during standby modes 失效
公开(公告)号：US06903994B1
公开(公告)日：2005-06-07
申请号：US10713520
申请日：2003-11-14
申请人： Aaron M. Schoenfeld
发明人： Aaron M. Schoenfeld
IPC分类号： G11C5/00 , G11C5/14 , G11C7/00 , G11C11/406 , G11C11/4074
CPC分类号： G11C11/40615 , G11C5/14 , G11C7/1045 , G11C11/406 , G11C11/4074 , G11C2207/2227 , G11C2211/4067
摘要： A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs for further reducing the power to portions of the memory device.

9. 发明授权

US06753482B1 Semiconductor component with adjustment circuitry 有权
标题翻译：具有调节电路的半导体元件
公开(公告)号：US06753482B1
公开(公告)日：2004-06-22
申请号：US10140340
申请日：2002-05-06
申请人： Aaron M. Schoenfeld , David J. Corisis , Tyler J. Gomm
发明人： Aaron M. Schoenfeld , David J. Corisis , Tyler J. Gomm
IPC分类号： H01R1204
CPC分类号： H01L24/06 , H01L23/3128 , H01L23/49838 , H01L23/5382 , H01L23/66 , H01L24/48 , H01L24/97 , H01L2224/04042 , H01L2224/05553 , H01L2224/05599 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/05657 , H01L2224/05666 , H01L2224/05669 , H01L2224/05678 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/06136 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/85424 , H01L2224/85444 , H01L2224/85455 , H01L2224/8547 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/30107 , Y10T29/49002 , Y10T29/49004 , Y10T29/49105 , Y10T29/49107 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49156 , Y10T29/49162 , Y10T29/49222 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.
摘要翻译：半导体部件包括调整电路，其被配置为调整部件或其元件的选定的物理和电特性以及该部件的输入/输出配置。该组件包括半导体管芯，附着到管芯的衬底以及衬底上的端子触点。调节电路包括与管芯和端子触点电连通的导体和可编程链路，例如熔丝或反熔丝。调节电路还可以包括电容器和电感导体。使用激光或编程信号，可编程链路可以被置于选定的状态（例如，短路或开路）。一种用于制造组件的方法包括以下步骤：形成调整电路，然后将可编程链路放置在所选择的状态以实现所选择的调整。

10. 发明授权

US06693472B2 Method and circuit for adjusting the timing of output data based on an operational mode of output drivers 失效
标题翻译：基于输出驱动器的操作模式来调整输出数据的时序的方法和电路
公开(公告)号：US06693472B2
公开(公告)日：2004-02-17
申请号：US10243279
申请日：2002-09-12
申请人： Vladimir Mikhalev , Aaron M. Schoenfeld , Daniel B. Penney , William C. Waldrop
发明人： Vladimir Mikhalev , Aaron M. Schoenfeld , Daniel B. Penney , William C. Waldrop
IPC分类号： H03L706
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , H03L7/0812
摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
摘要翻译：延迟锁定环路调整响应于外部时钟信号而产生的时钟信号的延迟。时钟信号被施加到输出缓冲器以对缓冲器进行时钟，使得来自缓冲器的数据或时钟信号与外部时钟信号同步。响应于分别具有第一和第二逻辑状态的输出驱动强度位，输出缓冲器以全驱动和降低驱动模式工作。延迟锁定环路响应于输出驱动强度位的状态来调整时钟信号的延迟，以在两种操作模式期间保持来自缓冲器的数据或时钟信号同步。

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