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1. 发明授权

US3909703A Low power gate switching device for triacs 失效
标题翻译：用于三端双向可控硅的低功耗门极开关器件
公开(公告)号：US3909703A
公开(公告)日：1975-09-30
申请号：US48939874
申请日：1974-07-17
申请人： AMERICAN MICRO SYST
发明人： BRADDOCK WALTER B
IPC分类号： H02M1/08 , G05F1/445 , G05F3/04
CPC分类号： G05F1/445
摘要： A high gate current thyrister device is controlled by low current digital integrated MOS circuitry which samples alternating current supplied to the thyrister to detect zero voltage cross over points and converts each cross over point to a digital signal pulse which is then delayed until the ac waveform has passed beyond the zero voltage cross over point just far enough so that when the digital pulse is applied to the control gate of the thyrister self conduction thereof results while its duty cycle is maximized. Control of the thyrister duty cycle may be accomplished by delaying the digital control pulse for a predetermined time until the desired fractional amount of duty cycle to be omitted has elapsed, whereupon the delayed pulse is then applied to the control gate and produces self conduction of the thyrister.
摘要翻译：高栅极电流可控硅器件由低电流数字集成MOS电路控制，低电流数字集成MOS电路对提供给可控硅的交流电进行采样，以检测零点电压交叉点，并将每个交叉点转换成数字信号脉冲，然后将其延迟直到交流波形超过零电压交叉点足够远，使得当数字脉冲施加到可控硅的控制栅极时，其自身的传导结果在其占空比最大化的同时。可以通过将数字控制脉冲延迟预定时间直到所需省略的期望的占空比分数已经过去，从而将延迟的脉冲施加到控制门并产生自理查德。

2. 发明授权

US3674917A Frequency selecting system 失效
标题翻译：频率选择系统
公开(公告)号：US3674917A
公开(公告)日：1972-07-04
申请号：US3674917D
申请日：1971-02-24
申请人： AMERICAN MICRO SYST
发明人： MYERS WILLIAM N JR
IPC分类号： G06F3/00 , H04L7/00 , H04L15/00
CPC分类号： H04L7/00 , G06F3/00
摘要： This invention relates to a computer system for selecting the rate of presentation of a plurality of digital signals from a particular number of rates stored in the computer. During a particular number of digital signals such as the first two digital signals in a sequence, clock signals are introduced to a counter. Every time that the counter overflows, the frequency of the clock signals is reduced by an arithmetic factor and a count is inserted into the counter in accordance with the reduction in the frequency of the clock signals. At the end of the particular number of digital signals, the computer determines the rate of the digital signals from the count in the counter and the frequency of the clock signals and selects, from the particular number of rates stored in the computer, the rate closest to the determined rate. The computer then resets the count in the counter and selects the frequency of the clock signals in accordance with the selected rate of the digital signals.

3. 发明授权

US3663921A Receptacle for connecting semiconductors to a circuit board 失效
标题翻译：用于将半导体连接到电路板的接口
公开(公告)号：US3663921A
公开(公告)日：1972-05-16
申请号：US3663921D
申请日：1970-07-07
申请人： AMERICAN MICRO SYST
发明人： RICHARD DONALD F
IPC分类号： H05K7/10 , H05K1/02
CPC分类号： H05K7/1076
摘要： A receptacle for installation on one surface of a circuit board for supporting a semiconductor package of the type having bonding pads along one side and providing an interconnection being the package and the circuit board. The receptacle has a generally channel-shaped planform with a series of contact members spaced apart along a central body section. The contact members extend upwardly and outwardly from one side and register with bonding pads of the package. The lower ends of the contact members extend through the circuit board for connection with lead terminals on its other surface.
摘要翻译：一种用于安装在电路板的一个表面上的插座，用于沿着一侧支撑具有接合焊盘的类型的半导体封装，并提供作为封装和电路板的互连。容器具有大致通道形状的平面形状，具有沿着中心主体部分间隔开的一系列接触构件。接触构件从一侧向上和向外延伸并与封装的焊盘对准。接触构件的下端延伸穿过电路板，用于与其另一表面上的引线端子连接。

4. 发明授权

US3651334A Two-phase ratioless logic circuit with delayless output 失效
标题翻译：具有无延迟输出的两相分级逻辑电路
公开(公告)号：US3651334A
公开(公告)日：1972-03-21
申请号：US3651334D
申请日：1969-12-08
申请人： AMERICAN MICRO SYST
发明人： THOMPSON ANDREW V , HERLEIN RICHARD F
IPC分类号： H03K19/096 , H03K17/60
CPC分类号： H03K19/096
摘要： A logic circuit providing a delayless inversion of a data input signal which employs one clock phase for simultaneously precharging the output node and discharging a storage node that is the gate of a logic transistor and is connected to the data input through a gating transistor. A second clock phase causes the gating transistor to conduct and, depending on the data input signal, the input node either remains discharged or is charged negative, thereby causing the output node to either remain negative or to be discharged through the logic transistor.
摘要翻译：一种提供数据输入信号的无延迟反转的逻辑电路，其采用一个时钟相位，以同时对输出节点进行预充电并对作为逻辑晶体管的栅极的存储节点进行放电，并通过门控晶体管连接到输入的数据。第二时钟相位导致门控晶体管导通，并且根据数据输入信号，输入节点或者保持放电或者被负电，从而使输出节点保持为负或通过逻辑晶体管放电。

5. 发明授权

US3582674A Logic circuit 失效
公开(公告)号：US3582674A
公开(公告)日：1971-06-01
申请号：US3582674D
申请日：1967-08-23
申请人： AMERICAN MICRO SYST
发明人： POUND ALAN E
IPC分类号： H03K3/037 , H03K5/135 , H03K19/0185 , H03K19/096 , H03K19/173 , H03K19/08
CPC分类号： H03K19/018557 , H03K3/037 , H03K5/135 , H03K19/096 , H03K19/1733
摘要： A logic circuit is disclosed comprised of two separate but connectable sections, namely a complex gate section and a delay section. The gate section has five input terminals for receiving data and/or control input signals and a single output, the delay section having a single input and two outputs providing a 1-bit delay output and a complemented 1-bit delay. By means of various interconnections the circuit can provide a wide range of functional devices including various flip-flop arrangements with clear and load capabilities.

6. 发明授权

US3754278A Thermal printing system 失效
标题翻译：热打印系统
公开(公告)号：US3754278A
公开(公告)日：1973-08-21
申请号：US3754278D
申请日：1971-12-01
申请人： AMERICAN MICRO SYST
发明人： BORDEN H
IPC分类号： G06F15/02 , B41J2/32 , B41J2/345 , G06K15/10 , G01D15/10
CPC分类号： B41J2/345
摘要： A thermal printer for electronic calculators or other computing devices comprises a multi-layer print head with a metallized layer on one outer surface formed as a series of master characters each comprised of a plurality of segments which are electrical resistance elements that extend between end contacts. These contacts are connected to an intermediate or buried metallized layer within the ceramic body which in turn provides for interconnections with another metallization layer including input ground and driver lead contact pads formed on the other outer surface of the ceramic body. A logic control sub-system for the printer receives signals from a driver output such as a calculator computing circuit and thereby controls the electrical energy furnished to the various character segments on the print head to heat them and produce the appropriate printout when the print head is in contact with heat sensitive paper. This subsystem stores the information received from the driver output and then utilizes the stored information in a multiplexing or time sharing arrangement to energize sequentially groups of preselected segment portions of all the master characters during a series of separate consecutive time periods of the print cycle.
摘要翻译：用于电子计算器或其他计算设备的热敏打印机包括多层打印头，其在一个外表面上具有金属化层，形成为一系列主要字符，每个主要字符由多个段组成，这些段是在端部触点之间延伸的电阻元件。这些触点连接到陶瓷体内的中间或埋入的金属化层，其又提供与包括形成在陶瓷体的另一外表面上的输入接地和驱动器引线接触焊盘的另一金属化层的互连。用于打印机的逻辑控制子系统从诸如计算器计算电路的驱动器输出接收信号，从而控制提供给打印头上的各个字符段的电能以加热它们，并且当打印头是与热敏纸接触。该子系统存储从驱动器输出接收到的信息，然后利用多路复用或时间共享装置中存储的信息来在打印周期的一系列分开的连续时间段期间依次激励所有主字符的预选段部分的组。

7. 发明授权

US3626202A Logic circuit 失效
公开(公告)号：US3626202A
公开(公告)日：1971-12-07
申请号：US3626202D
申请日：1970-07-13
申请人： AMERICAN MICRO SYST
发明人： POUND ALAN E
IPC分类号： H03K3/037 , H03K5/135 , H03K19/0185 , H03K19/096 , H03K19/173 , H03K19/08
CPC分类号： H03K19/018557 , H03K3/037 , H03K5/135 , H03K19/096 , H03K19/1733
摘要： A logic circuit is disclosed comprised of two separate but connectable sections, namely a complex gate section and a delay section. The gate section has five input terminals for receiving data and/or control input signals and a single output, the delay section having a single input and two outputs providing a one-bit delay output and a complemented one-bit delay. By means of various interconnections the circuit can provide a wide range of functional devices including various flip-flop arrangements with clear and load capabilities.

8. 发明授权

US3924265A Low capacitance V groove MOS NOR gate and method of manufacture 失效
公开(公告)号：US3924265A
公开(公告)日：1975-12-02
申请号：US39266873
申请日：1973-08-29
申请人： AMERICAN MICRO SYST
发明人： RODGERS THURMAN JOHN
IPC分类号： H01L21/764 , H01L21/8234 , H01L27/07 , H01L27/088 , H01L29/00 , H01L29/423 , H01L29/78 , H03K19/0944 , H01L27/04 , H01L21/467
CPC分类号： H03K19/09441 , H01L27/0738 , H01L27/088 , H01L29/00 , H01L29/4236 , Y10S148/008 , Y10S148/049 , Y10S148/051 , Y10S148/053 , Y10S148/085 , Y10S148/117
摘要： An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.

9. 发明授权

US3799649A Haze barrier for liquid crystal display 失效
标题翻译：用于液晶显示器的HAZE BARRIER
公开(公告)号：US3799649A
公开(公告)日：1974-03-26
申请号：US33859073
申请日：1973-03-06
申请人： AMERICAN MICRO SYST
发明人： CARLYLE J
IPC分类号： G02F1/1341 , G02F1/13
CPC分类号： G02F1/1341
摘要： A liquid crystal display device comprised of a pair of spaced apart glass plates joined together by a peripheral seal to form a planar cavity for liquid crystal material utilizes an internal barrier spaced from one end of the seal having a plugged opening. The barrier helps to prevent the plug from being pushed out and also reduces the migration of haze forming impurities from the plug into the cavity.
摘要翻译：由一对间隔开的玻璃板构成的液晶显示装置，其通过周边密封件连接在一起以形成用于液晶材料的平面空腔，利用与具有堵塞开口的密封件的一端隔开的内部屏障。屏障有助于防止插头被推出，并且还减少了从插头将杂质形成杂质迁移到空腔中的迁移。

10. 发明授权

US3783306A Low power ring counter 失效
标题翻译：低功率环计数器
公开(公告)号：US3783306A
公开(公告)日：1974-01-01
申请号：US3783306D
申请日：1972-04-05
申请人： AMERICAN MICRO SYST
发明人： HOFFMANN K
IPC分类号： H03K23/52 , H03K23/54 , H03K21/00 , H03K19/08
CPC分类号： H03K23/54
摘要： A ring counter that is operable by a relatively low power level comprises master and slave flip-flop sections having n stages connected in parallel to alternating clock means. Each stage has a series of AND-NOR gates including one AND-NOR gate used as a reset and connected to the other parts of the section. The alternating clocks for the master and slave sections are applied to advance the counter by shifting the direct current path from stage to stage. Each stage is self gated so that power is consumed only when that stage or flip-flop is being enabled.
摘要翻译：可由相对低功率电平操作的环形计数器包括具有与交替时钟装置并联连接的n个级的主从触发器部分。每个级具有一系列与或非门，包括一个与或非门作为复位并连接到该部分的其他部分。通过将直流路径从一级转移到另一级，通过主机和从机部分的交替时钟被应用来提前计数器。每个阶段都是自动门控，只有当该阶段或触发器被使能时才会消耗功耗。

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