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1. 发明授权

US08119470B2 Mitigation of gate to contact capacitance in CMOS flow 有权
标题翻译：栅极接触电容在CMOS流中的缓解
公开(公告)号：US08119470B2
公开(公告)日：2012-02-21
申请号：US11726253
申请日：2007-03-21
申请人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
发明人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
IPC分类号： H01L21/338 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/7833 , H01L21/76804 , H01L21/76897 , H01L29/6656 , H01L29/6659 , Y02P80/30
摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.
摘要翻译：主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。这种电容至少是不利的，因为它可以抑制晶体管的切换速度。因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

2. 发明授权

US07396728B2 Methods of improving drive currents by employing strain inducing STI liners 有权
标题翻译：应用感应STI衬垫改善驱动电流的方法
公开(公告)号：US07396728B2
公开(公告)日：2008-07-08
申请号：US11170501
申请日：2005-06-29
申请人： Ajith Varghese , Narendra Singh Mehta , Jonathan McAulay Holt
发明人： Ajith Varghese , Narendra Singh Mehta , Jonathan McAulay Holt
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.
摘要翻译：一种方法形成包括选择性地将应变引入到NMOS和PMOS器件的有源区的隔离结构的半导体器件。在半导体体上形成硬掩模层。在暴露并限定隔离区域的硬掩模层上形成抗蚀剂层。图案化硬掩模层，并使用硬掩模层作为掩模形成沟槽区域。在PMOS区域的沟槽区域内形成有对PMOS区域的有源区域产生压缩应变的氧化物沟槽衬垫。在NMOS沟槽区域内形成氮化物沟槽衬垫，其将拉伸应变引入NMOS区域的有源区。

3. 发明申请

US20080006886A1 Semiconductor Device Manufactured Using a Non-Contact Implant Metrology 有权
标题翻译：使用非接触式种植体计量制造的半导体器件
公开(公告)号：US20080006886A1
公开(公告)日：2008-01-10
申请号：US11559271
申请日：2006-11-13
申请人： Narendra Mehta , Ajith Varghese , Benjamin Moser
发明人： Narendra Mehta , Ajith Varghese , Benjamin Moser
IPC分类号： H01L21/425 , H01L29/78
CPC分类号： H01L21/26513 , H01L21/31155 , H01L22/14
摘要： A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a calibration substrate. A dopant is implanted into the dielectric layer. Charge is deposited on a surface of the dielectric layer, and voltage on the surface is measured. An electrical characteristic of the dielectric layer is determined, and a doping level of the dielectric layer is determined from the electrical characteristic. The electrical characteristic is associated with an operating set-point of the ion implant process. The calibrated ion implant process is used to implant the dopant into a semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，包括校准离子注入工艺。校准包括在校准基板上形成电介质层。将掺杂剂注入电介质层。电荷沉积在电介质层的表面上，并且测量表面上的电压。确定电介质层的电特性，根据电气特性确定电介质层的掺杂程度。电特性与离子注入工艺的操作设定点相关联。校准离子注入工艺用于将掺杂剂注入到半导体衬底中。

4. 发明申请

US20070004118A1 Methods of improving drive currents by employing strain inducing STI liners 有权
标题翻译：应用感应STI衬垫改善驱动电流的方法
公开(公告)号：US20070004118A1
公开(公告)日：2007-01-04
申请号：US11170501
申请日：2005-06-29
申请人： Ajith Varghese , Narendra Mehta , Jonathan Holt
发明人： Ajith Varghese , Narendra Mehta , Jonathan Holt
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76224 , H01L21/823878
摘要： A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.
摘要翻译：一种方法形成包括选择性地将应变引入到NMOS和PMOS器件的有源区的隔离结构的半导体器件。在半导体体上形成硬掩模层。在暴露并限定隔离区域的硬掩模层上形成抗蚀剂层。图案化硬掩模层，并使用硬掩模层作为掩模形成沟槽区域。在PMOS区域的沟槽区域内形成有对PMOS区域的有源区域产生压缩应变的氧化物沟槽衬垫。在NMOS沟槽区域内形成氮化物沟槽衬垫，其将拉伸应变引入NMOS区域的有源区。

5. 发明授权

US07838370B2 Highly selective liners for semiconductor fabrication 有权
标题翻译：用于半导体制造的高选择性衬垫
公开(公告)号：US07838370B2
公开(公告)日：2010-11-23
申请号：US11965633
申请日：2007-12-27
申请人： Narendra Singh Mehta , Wayne Anthony Bather , Ajith Varghese
发明人： Narendra Singh Mehta , Wayne Anthony Bather , Ajith Varghese
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L29/7846
摘要： A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein.
摘要翻译：公开了一种用于制造隔离结构的方法，其在蚀刻二氯硅烷（DCS）氮化物层期间保护隔离结构。该方法涉及在隔离沟槽内形成双 - （叔丁基氨基）硅烷基氮化物衬垫层，与DCS氮化物相比，其表现出比氮化物蚀刻溶液更强的五倍的耐受性，从而允许保护免受非预期的过蚀刻。双 - （叔丁基氨基）硅烷基氮化物层也在沟槽区域上施加更大的拉伸应变，导致有源区域的载流子迁移率增加，从而增加嵌入其中的NMOS晶体管的性能。

6. 发明授权

US07723173B2 Low temperature polysilicon oxide process for high-K dielectric/metal gate stack 有权
标题翻译：用于高K电介质/金属栅极叠层的低温多晶硅氧化物工艺
公开(公告)号：US07723173B2
公开(公告)日：2010-05-25
申请号：US12400253
申请日：2009-03-09
申请人： Ajith Varghese , James J. Chambers
发明人： Ajith Varghese , James J. Chambers
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28097 , H01L21/28247 , H01L21/32105 , H01L21/3211 , H01L21/823842 , H01L21/823864 , H01L29/4958 , H01L29/4975
摘要： A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NH3 annealing. The oxide provides a coating over the top and sides of the stacks to protect metal and interfaces from oxidation.
摘要翻译：公开了一种用于在制造集成电路器件的高k电介质/金属栅极堆叠中防止氧化的方法。在一个详细的实施例中，PMOS区叠层具有氮化硅化铪，钨，氮化钽和多晶硅层。 NMOS区域叠层具有氮化硅化铪，硅化钨，氮化钽和多晶硅层。使用低温紫外臭氧氧化法或使用解耦等离子体氮化或NH 3退火的等离子体氮化将沉积在堆叠上的薄多晶硅层转化为氧化物。氧化物在堆叠的顶部和侧面提供涂层以保护金属和界面免受氧化。

7. 发明申请

US20090170346A1 LOW TEMPERATURE POLYSILICON OXIDE PROCESS FOR HIGH-K DIELECTRIC/METAL GATE STACK 有权
标题翻译：用于高K电介质/金属栅极堆栈的低温多聚氧化物过程
公开(公告)号：US20090170346A1
公开(公告)日：2009-07-02
申请号：US12400253
申请日：2009-03-09
申请人： Ajith Varghese , James J. Chambers
发明人： Ajith Varghese , James J. Chambers
IPC分类号： H01L21/473 , H01L21/4763
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28097 , H01L21/28247 , H01L21/32105 , H01L21/3211 , H01L21/823842 , H01L21/823864 , H01L29/4958 , H01L29/4975
摘要： A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NH3 annealing. The oxide provides a coating over the top and sides of the stacks to protect metal and interfaces from oxidation.
摘要翻译：公开了一种用于在制造集成电路器件的高k电介质/金属栅极堆叠中防止氧化的方法。在一个详细的实施例中，PMOS区叠层具有氮化硅化铪，钨，氮化钽和多晶硅层。 NMOS区域叠层具有氮化硅化铪，硅化钨，氮化钽和多晶硅层。使用低温紫外臭氧氧化法或使用解耦等离子体氮化或NH 3退火的等离子体氮化将沉积在堆叠上的薄多晶硅层转化为氧化物。氧化物在堆叠的顶部和侧面提供涂层以保护金属和界面免受氧化。

8. 发明申请

US20080246099A1 LOW TEMPERATURE POLY OXIDE PROCESSES FOR HIGH-K/METAL GATE FLOW 审中-公开
标题翻译：用于高K /金属栅流的低温聚氧化物工艺
公开(公告)号：US20080246099A1
公开(公告)日：2008-10-09
申请号：US11697993
申请日：2007-04-09
申请人： Ajith Varghese , James J. Chambers
发明人： Ajith Varghese , James J. Chambers
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28097 , H01L21/28247 , H01L21/32105 , H01L21/3211 , H01L21/823842 , H01L21/823864 , H01L29/4958 , H01L29/4975
摘要： An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon coating using UV O3 low temperature oxidation and plasma nitridation using either decoupled plasma nitridation or NH3 annealing.
摘要翻译：公开了一种集成电路装置，其包括容易氧化的特征。在易于氧化的特征上使用多氧化物涂层以保护易于氧化的特征被氧化。可以使用各种方法形成多氧化物涂层，包括使用分离等离子体氮化或NH 3的低温氧化和等离子体氮化，使用UV O 3 N 3转化合金 - 硅涂层， SUB>退火。

9. 发明授权

US07384861B2 Strain modulation employing process techniques for CMOS technologies 有权
标题翻译：采用CMOS技术的工艺技术进行应变调制
公开(公告)号：US07384861B2
公开(公告)日：2008-06-10
申请号：US11183348
申请日：2005-07-18
申请人： Narendra Singh Mehta , Wayne Anthony Bather , Ajith Varghese
发明人： Narendra Singh Mehta , Wayne Anthony Bather , Ajith Varghese
IPC分类号： H01L21/425
CPC分类号： H01L21/823807 , H01L21/265 , H01L21/823878 , H01L29/7843 , H01L29/7846
摘要： A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the first and second regions. A mask is then formed that exposes the second region and covers the first region. A material is selected for a modification implant and the selected material is implanted into the second region thereby converting a portion of the modifiable tensile strain inducing layer into a compressive strain inducing layer within the PMOS region.
摘要翻译：一种方法形成包括可修改的应变诱导层的半导体器件。提供半导体本体。识别半导体主体的第一和第二区域。在第一和第二区域内的器件上形成可修改的拉伸应变诱导层。然后形成露出第二区域并覆盖第一区域的掩模。选择材料用于修改植入物，并且将所选择的材料注入第二区域，从而将可修改的拉伸应变诱导层的一部分转化为PMOS区域内的压缩应变诱导层。

10. 发明申请

US20070207572A1 CMOS Device Having Different Amounts of Nitrogen in the NMOS Gate Dielectric Layers and PMOS Gate Dielectric Layers 有权
标题翻译：在NMOS栅极电介质层和PMOS栅介质层中具有不同氮含量的CMOS器件
公开(公告)号：US20070207572A1
公开(公告)日：2007-09-06
申请号：US11745930
申请日：2007-05-08
申请人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
IPC分类号： H01L21/82
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

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