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    • 1. 发明申请
    • METHOD AND SYSTEM FOR MANAGING CREDIT-RELATED AND EXCHANGE-RATE RELATED RISK
    • 用于管理信用相关和交换率相关风险的方法和系统
    • WO2004001523A2
    • 2003-12-31
    • PCT/IB2003/003221
    • 2003-06-20
    • FUNG, Ka, Shun, Kevin
    • FUNG, Ka, Shun, Kevin
    • G06F
    • G06Q40/04G06Q30/08G06Q40/00G06Q40/025
    • A method and system for managing risk for contracts offered for trading in systems is disclosed. A complete set of contracts includes the contracts, each of which matures upon events) occurring. The complete set guarantees at least an initial settlement value at at least one particular time. The complete set also corresponds to a settlement value, which is based upon the initial settlement value and an, preferably, interest rate effect, if any. A winning contract pays a notional upon maturing. Rate differentials) between systems, and hedging costs exist. In one aspect, the method and system include determining whether a matching trade in a second system for a trade in a first system is possible, determining whether conducting the trades is profitable and, if so, performing these trades. In another aspect, the method and system determine whether individually selling the contracts) is profitable given the rate differential. If so, the method and system also include obtaining the complete set and individually selling the contract(s). In another aspect the method and system include determining whether assembling the complete set is profitable given the rate differential. If so, the method and system include assembling the complete set and exchanging the complete set for the settlement value.
    • 披露了一种用于管理系统交易合同风险的方法和系统。 一整套合同包括发生的合同,每个合同都会在事件中成熟。 至少在一个特定时间内,完整的集合至少保证初始结算价值。 完整的集合也对应于一个结算值,该结算值基于初始结算值,最好是利率效应(如果有的话)。 获胜合同在成熟时支付名义。 价格差异),存在套期保值成本。 在一个方面,所述方法和系统包括确定第一系统中的交易的第二系统中的匹配交易是否可能,确定进行交易是否是有利的,并且如果是,则执行这些交易。 另一方面,方法和系统确定是否单独出售合同)在利率差异的情况下是有利可图的。 如果是这样,该方法和系统还包括获得整套和单独出售合同。 在另一方面,方法和系统包括确定组合整套在给定速率差异时是否有利。 如果是这样,方法和系统包括组合整套和交换结算值的整套。
    • 3. 发明授权
    • Key cache management through multiple localities
    • 通过多个地方进行密钥缓存管理
    • US07590845B2
    • 2009-09-15
    • US10744441
    • 2003-12-22
    • Charles Douglas BallRyan Charles CathermanJames Patrick HoffJames Peter Ward
    • Charles Douglas BallRyan Charles CathermanJames Patrick HoffJames Peter Ward
    • H04L9/14G06F12/08
    • H04L9/0894
    • A method for a plurality of key cache managers for a plurality of localities to share cryptographic key storage resources of a security chip, includes: loading an application key into the key storage; and saving a restoration data for the application key by a key cache manager, where the restoration data can be used by the key cache manager to re-load the application key into the key storage if the application key is evicted from the key storage by another key cache manager. The method allows each of a plurality of key cache managers to recognize that its key had been removed from the security chip and to restore its key. The method also allows each key cache manager to evict or destroy any key currently loaded on the security chip without affecting the functionality of other localities.
    • 一种用于多个地区的多个密钥高速缓存管理器用于共享安全芯片的加密密钥存储资源的方法,包括:将应用密钥加载到密钥存储器中; 并且由密钥高速缓存管理器保存用于应用密钥的恢复数据,其中如果应用密钥从另一个密钥存储器被逐出,密钥高速缓存管理器可以使用恢复数据将应用密钥重新加载到密钥存储器中 密钥缓存管理器。 该方法允许多个密钥高速缓存管理器中的每一个识别出其密钥已经从安全芯片中移除并恢复其密钥。 该方法还允许每个密钥缓存管理器驱逐或销毁安全芯片上当前加载的任何密钥,而不影响其他地方的功能。
    • 4. 发明授权
    • Multi-level variable-resistor line driver
    • 多电平可变电阻线路驱动器
    • US07532048B1
    • 2009-05-12
    • US11738864
    • 2007-04-23
    • Ramin ShiraniRamin Farjadrad
    • Ramin ShiraniRamin Farjadrad
    • H03K3/00
    • H04L25/4917H03K17/6871H03K2217/0036H04L25/028
    • The line driver circuit is provided that includes a first pull-up variable resistor connected between a first power supply and the first output terminal, a second pull-up variable resistor connected between the first power supply and the second output terminal, a first pull-down variable resistor connected between a second power supply and the first output terminal, a second pull-down variable resistor connected between the second power supply and the second output terminal, a floating variable resistor connected between the first output terminal and the second output terminal, and coder logic to adjust an output voltage across the first output terminal and the second output terminal by varying a resistance of one or more of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor in response to received data bits.
    • 提供线路驱动器电路,其包括连接在第一电源和第一输出端子之间的第一上拉可变电阻器,连接在第一电源和第二输出端子之间的第二上拉可变电阻器, 连接在第二电源和第一输出端子之间的下降可变电阻器,连接在第二电源和第二输出端子之间的第二下拉可变电阻器,连接在第一输出端子和第二输出端子之间的浮动可变电阻器, 以及编码器逻辑,通过改变所述浮动可变电阻器,所述第一上拉可变电阻器,所述第二上拉可变电阻器,所述第一上拉可变电阻器中的一个或多个的电阻来调整所述第一输出端子和所述第二输出端子两端的输出电压 下拉可变电阻器和第二下拉可变电阻器,以响应于接收到的数据位。
    • 10. 发明授权
    • Method for reducing power consumption with configurable latches and registers
    • 用配置锁存器和寄存器降低功耗的方法
    • US07474123B1
    • 2009-01-06
    • US11839829
    • 2007-08-16
    • Michael Raymond Miller
    • Michael Raymond Miller
    • G06F7/38H03K19/173
    • H03K19/0016
    • Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second latches, and the second enable input enables and disables the second latch and does not affect the first latch. The first enable input has an earlier required signal arrival time than the second enable input to be effective for a particular clock cycle. A circuit configures the sequential logic device at operating time to consume less power during a lower frequency of operation of the sequential logic device, and to consume more power during a higher frequency of operation.
    • 锁存器和类似电子设备的功耗降低。 一方面,用于配置顺序逻辑的功耗的装置包括顺序逻辑器件,其包括第一锁存器,第二锁存器以及第一和第二使能输入。 第一使能输入启用和禁用第一和第二锁存器,第二使能输入使能和禁止第二个锁存器,并且不影响第一个锁存器。 第一使能输入具有比第二使能输入更早要求的信号到达时间,以在特定时钟周期内有效。 一个电路在顺序逻辑器件的较低工作频率下,将顺序逻辑器件配置在工作时间以消耗更少的功率,并在更高的工作频率下消耗更多的功率。