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1. 发明申请

WO2007008903A2 MEMORY CELL COMPRISING A THIN FILM THREE-TERMINAL SWITCHING DEVICE HAVING A METAL SOURCE AND/OR DRAIN REGION 审中-公开
标题翻译：包含金属源和/或排水区域的薄膜三端开关装置的存储单元
公开(公告)号：WO2007008903A2
公开(公告)日：2007-01-18
申请号：PCT/US2006/026898
申请日：2006-07-11
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
发明人： SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
IPC分类号： H01L21/8247 , H01L27/11 , H01L27/115 , H01L27/06
CPC分类号： H01L27/1203 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L21/84 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L29/685 , H01L29/786 , H01L29/8605 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： A nonvolatile memory cell comprising a switchable resistor memory element and a thin-film three- terminal switching device, preferably a MOSFET, in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high-resistance state and a low-resistance state. It is switched between the two states, and its resistance state (and thus the data state of the cell) is sensed by providing appropriate current through the three-terminal switching device. Preferred embodiments of the present invention include a highly dense monolithic three dimensional memory array in which multiple memory levels of such memory cells are formed above a single substrate such as a monocrystalline silicon wafer.
摘要翻译：一种非易失性存储单元，包括可切换电阻存储元件和薄膜三端开关器件，优选地是串联的MOSFET。可切换电阻存储元件具有至少两个稳定的电阻状态的特性，例如高电阻状态和低电阻状态。它在两个状态之间切换，并且通过提供通过三端开关装置的适当电流来感测其电阻状态（以及因此的小区的数据状态）。本发明的优选实施例包括高密度单片三维存储器阵列，其中这种存储器单元的多个存储器级别形成在诸如单晶硅晶片的单个衬底上方。

2. 发明申请

WO2006104877A3 METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE 审中-公开
公开(公告)号：WO2006104877A3
公开(公告)日：2006-10-05
申请号：PCT/US2006/010757
申请日：2006-03-24
申请人： SANDISK 3D, LLC , DUNTON, Samuel V. , RAGHURAM, Usha , PETTI, Christopher J.
发明人： DUNTON, Samuel V. , RAGHURAM, Usha , PETTI, Christopher J.
IPC分类号： H01L21/768 , H01L21/8246
摘要： A substantially planar surface coexposes conductive or semiconductor features (300) and a dielectric etch, stop material (120). A second dielectric material (107), different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric (108) such, as oxide, recessing the oxide, filling with the dielectric etch stop material such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.

3. 发明申请

WO2006130800A3 REWRITEABLE MEMORY CELL COMPRISING A TRANSISTOR AND RESISTANCE-SWITCHING MATERIAL IN SERIES 审中-公开
公开(公告)号：WO2006130800A3
公开(公告)日：2006-12-07
申请号：PCT/US2006/021372
申请日：2006-06-01
申请人： SANDISK 3D LLC , PETTI, Christopher, J. , SCHEUERLEIN, Roy, E.
发明人： PETTI, Christopher, J. , SCHEUERLEIN, Roy, E.
IPC分类号： H01L27/00 , H01L45/00
摘要： A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance- switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed in a monocrystalline wafer substrate. In preferred embodiments the transistor may have' either a vertically oriented ch'annel or a laterally oriented channel. Either embodiment can be formed in a monolithic three dimensional memory array in which multiple memory levels can be formed above a single substrate, forming a highly dense nonvolatile memory array.

4. 发明申请

WO2006104817A2 METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES 审中-公开
标题翻译：在制造与导电特性接触时减少电介质覆盖物的方法
公开(公告)号：WO2006104817A2
公开(公告)日：2006-10-05
申请号：PCT/US2006/010520
申请日：2006-03-21
申请人： SANDISK 3D, LLC , PETTI, Christopher J.
发明人： PETTI, Christopher J.
IPC分类号： H01L21/768 , H01L27/102
CPC分类号： H01L21/768 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features.
摘要翻译：在本发明的第一优选实施例中，导电特征形成在第一电介质蚀刻停止层上，并且第二电介质材料沉积在导电特征之上和之间。在第一和第二电介质之间选择性的导电特征的通孔蚀刻将停止在电介质蚀刻停止层上，限制过蚀刻。在第二实施例中，多个导电特征以消减图案和蚀刻工艺形成，填充有电介质填充物，然后形成为与导电特征和电介质填充物共同构成的表面。电介质蚀刻停止层沉积在表面上，然后第三电介质覆盖电介质蚀刻停止层。当通过第三电介质蚀刻接触时，该选择性蚀刻停止在电介质蚀刻停止层上。第二蚀刻与导电特征接触。

5. 发明申请

WO2006078506A2 STRUCTURE AND METHOD FOR BIASING PHASE CHANGE MEMORY ARRAY FOR RELIABLE WRITING 审中-公开
标题翻译：用于偏移相位变化记忆阵列的可靠写入的结构和方法
公开(公告)号：WO2006078506A2
公开(公告)日：2006-07-27
申请号：PCT/US2006/000776
申请日：2006-01-11
申请人： MATRIX SEMICONDUCTOR, INC. , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： H01L29/02
CPC分类号： G11C11/21 , G11C13/0004 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L27/2481
摘要： A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
摘要翻译：具有包括二极管和相变材料的存储单元的存储器阵列通过将所有未选择的存储单元维持在反向偏置状态来可靠地编程。因此，泄漏低，并且确保没有未选择的存储器单元受到干扰。为了在顺序写入期间避免干扰未选择的存储单元，在选择新的位线和字线之前，先前选择的字线和位线被带到其未选择的电压。改进的电流镜结构控制相变材料的状态切换。

6. 发明申请

WO2006078505A2 A NON-VOLATILE MEMORY CELL COMPRISING A DIELECTRIC LAYER AND A PHASE CHANGE MATERIAL IN SERIES 审中-公开
标题翻译：包含电介质层和相变材料的非易失性存储元件系列
公开(公告)号：WO2006078505A2
公开(公告)日：2006-07-27
申请号：PCT/US2006/000774
申请日：2006-01-11
申请人： MATRIX SEMICONDUCTOR, INC. , SCHEUERLEIN, Roy E. , HERNER, S. Brad
发明人： HERNER, S. Brad
IPC分类号： H01L21/336
CPC分类号： G11C5/02 , G11C11/39 , G11C13/00 , G11C13/0004 , G11C13/0069 , G11C17/16 , G11C2013/008 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： The invention provides for a nonvolatile memory cell comprising a dielectric material in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. By applying high voltage across a dielectric layer, dielectric breakdown occurs, forming a low-resistance rupture region traversing the dielectric layer. This rupture region can serve to concentrate thermal energy in a phase-change memory cell. In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.
摘要翻译：本发明提供了一种非易失性存储单元，其包括与相变材料（例如硫族化物）串联的电介质材料。通过热法在硫族化物记忆中实现相变。将热能集中在相对较小的体积中有助于此相变。通过在介电层上施加高电压，发生电介质击穿，形成穿过介电层的低电阻断裂区域。该破裂区域可用于将热能集中在相变存储器单元中。在优选实施例中，这样的单元可以用在单片三维存储器阵列中。

7. 发明申请

WO2006130801A2 TFT CHARGE STORAGE MEMORY CELL HAVING HIGH-MOBILITY CORRUGATED CHANNEL 审中-公开
标题翻译： TFT充电存储单元具有高移动性通道
公开(公告)号：WO2006130801A2
公开(公告)日：2006-12-07
申请号：PCT/US2006/021373
申请日：2006-06-01
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/06 , G11C16/04 , H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , G11C16/0475 , H01L21/845 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1211 , H01L29/0649 , H01L29/1037 , H01L29/66833 , H01L29/785 , H01L29/7853 , H01L29/7854 , H01L29/78618 , H01L29/7881 , H01L29/792
摘要： A rewriteable nonvolatile memory cell having two bits per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive nanocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing additional isolation between the two storage regions. The channel region is deposited and is preferably formed of polycrystalline germanium or silicon-germanium. The memory cell of the present invention can be formed in memory arrays; in preferred embodiments, multiple memory levels are formed stacked above a single substrate.
摘要翻译：描述每个单元具有两个位的可重写非易失性存储单元。存储单元优选通过通过通道热电子注入方法将电荷存储在介电电荷存储层中或电隔离的导电纳米晶体中来进行操作。在优选实施例中，通道区域具有波纹形状，在两个存储区域之间提供额外的隔离。沟道区域被沉积并且优选地由多晶锗或硅 - 锗形成。本发明的存储单元可以形成在存储器阵列中; 在优选实施例中，在单个衬底上堆叠形成多个存储器级。

8. 发明申请

WO2006121924A2 HIGH-DENSITY NONVOLATILE MEMORY ARRAY FABRICATED AT LOW TEMPERATURE COMPRISING SEMICONDUCTOR DIODES 审中-公开
标题翻译：高密度非易失性存储器阵列在包含半导体二极管的低温下制作
公开(公告)号：WO2006121924A2
公开(公告)日：2006-11-16
申请号：PCT/US2006/017525
申请日：2006-05-05
申请人： SANDISK 3D LLC , HERNER, S. Brad , DUNTON, Samuel V.
发明人： HERNER, S. Brad , DUNTON, Samuel V.
IPC分类号： H01L27/06 , H01L27/102
CPC分类号： H01L27/1021 , H01L27/0688
摘要： A memory cell is described suitable for use in a high-density monolithic three dimensional memory array. In preferred embodiments of the memory cell, a semiconductor junction diode formed of germanium or a germanium alloy which can be crystallized at relatively low temperature is formed disposed between conductors. The use of a low-temperature material allows the conductors to be formed of copper or aluminum, both low-resistivity materials that provide adequate current at very small feature size, allowing for a highly dense stacked array.
摘要翻译：描述适合用于高密度单片三维存储器阵列的存储单元。在存储单元的优选实施例中，形成由锗或锗合金形成的可在较低温度下结晶的半导体结二极管，形成在导体之间。使用低温材料允许导体由铜或铝形成，这两种低电阻率材料都能以非常小的特征尺寸提供足够的电流，从而允许高度密集的堆叠阵列。

9. 发明申请

WO2006105326A1 MASKING OF REPEATED OVERLAY AND ALIGNMENT MARKS TO ALLOW REUSE OF PHOTOMASKS IN A VERTICAL STRUCTURE 审中-公开
标题翻译：重复覆盖和对准标记的掩蔽以允许在垂直结构中重新使用光刻胶
公开(公告)号：WO2006105326A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/011715
申请日：2006-03-31
申请人： SANDISK 3D, LLC , CHEN, Yung-Tin , PETTI, Christopher, J. , RADIGAN, Steven, J. , KUMAR, Tanmay
发明人： CHEN, Yung-Tin , PETTI, Christopher, J. , RADIGAN, Steven, J. , KUMAR, Tanmay
IPC分类号： G03F9/00 , G03F7/20 , H01L23/00
CPC分类号： H01L27/0688 , G03F7/70633 , G03F9/7084 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/5446
摘要： In formation of monolithic three dimensional memory arrays, a photomask may be used more than once. Reuse of a photomask creates second, third or more instances of reference marks used by the stepper to achieve alignment (alignment marks) and to measure alignment achieved (overlay marks) directly above prior instances of the same reference mark. The prior instances of the same reference mark may cause interference with the present instance of the reference mark, complicating alignment and measurement. Using the methods of the present invention, blocking structure is created vertically interposed between subsequent instances of the same reference mark, preventing interference.
摘要翻译：在形成单片三维存储器阵列时，可以使用光掩模多于一次。重新使用光掩模创建步进器使用的第二，第三或更多个参考标记实例，以实现对齐（对齐标记）并且直接在相同参考标记的先前实例之上测量对齐（覆盖标记）。相同参考标记的先前实例可能引起对参考标记的当前实例的干扰，使对准和测量复杂化。使用本发明的方法，垂直地插入相同参考标记的后续实例之间的阻挡结构，以防止干扰。

10. 发明申请

WO2006088689A3 METHOD FOR PATTERNING SUBMICRON PILLARS 审中-公开
公开(公告)号：WO2006088689A3
公开(公告)日：2006-08-24
申请号：PCT/US2006/004195
申请日：2006-02-07
申请人： SANDISK CORPORATION , RAGHURAM, Usha , KONEVECKI, Michael W.
发明人： RAGHURAM, Usha , KONEVECKI, Michael W.
IPC分类号： H01L21/8234
摘要： The present invention provides for a method to pattern and etch very small dimension pillars, for example in a memory array. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.

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