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1. 发明申请

WO2006038200A1 A RADIO COMMUNICATIONS GATEWAY AND RADIO COMMUNICATIONS TERMINAL 审中-公开
标题翻译：无线电通信网关和无线电通信终端
公开(公告)号：WO2006038200A1
公开(公告)日：2006-04-13
申请号：PCT/IB2005/053288
申请日：2005-10-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HUS, Olivier, J-M.
发明人： HUS, Olivier, J-M.
IPC分类号： H04L12/28
CPC分类号： H04W88/06 , H04W28/24 , H04W84/04 , H04W84/18 , H04W88/16 , H04W92/02
摘要： A mobile telephone 12 acts as a radio communications gateway between a 3G network 10 and a Bluetooth ® network 11. A video conference call in the 3G network 10 is relayed over the Bluetooth ® network 11 to and from a Bluetooth ® enabled laptop Personal Computer (PC) 13, which therefore acts as a radio communications terminal. A Channel Quality Indicator (CQI) received by the mobile terminal 12 with the video conference content over the 3G network 10 is transmitted by the mobile telephone 12 to the laptop PC 13 over the Bluetooth ® network 13 as a Pseudo-CQI (P-CQI). In this example, the P-CQI is sent in a FLOW control field of a header 40 of a Synchronous Connection Oriented (SCO) or extended SCO (eSCO) data packet of the Bluetooth ® network 11. A video conference driver application running on the laptop PC 13 is then able to alter the video conference call properties according to the value of the P-CQI, thus responding to call quality conditions in the 3G network 10.
摘要翻译：移动电话12充当3G网络10和蓝牙^{之间的无线电通信网关}

2. 发明申请

WO2006030375A1 BIAS CIRCUITS 审中-公开
标题翻译：偏差电路
公开(公告)号：WO2006030375A1
公开(公告)日：2006-03-23
申请号：PCT/IB2005/052991
申请日：2005-09-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PERTIJS, Michiel, A., P. , HUIJSING, Johan, H.
发明人： PERTIJS, Michiel, A., P. , HUIJSING, Johan, H.
IPC分类号： G05F3/20
CPC分类号： G01K7/015 , G05F3/205
摘要： A bias circuit for use in bandgap voltage reference circuits and temperature sensors comprises a pair of transistors (Q,, Q2), the first of which (Q1) is arranged to be biased at an emitter current lbias, and the second of which (Q2) is arranged to be biased at an emitter current of m.lbi as . The circuit is arranged such that the difference between the base-emitter voltages of the transistors is generated in part across a first resistance means having a value Rbias and in use carrying a bias current equal to lbias and in part across a second resistance means of value substantially equal to Rbias/m and in use carrying a current equal to the base current of the second transistor. This results in use in a bias current I bias which, when used to bias a substrate bipolar transistor via its emitter, produces a collector current therefrom which is substantially PTAT and a base-emitter voltage which is substantially independent of the forward current gain of the substrate bipolar transistor.
摘要翻译：用于带隙电压参考电路和温度传感器的偏置电路包括一对晶体管（Q i，

3. 发明申请

WO2006030373A1 PULSE WIDTH MODULATED NOISE SHAPER AND RELATED METHOD 审中-公开
标题翻译：脉冲宽度调制噪声形状及相关方法
公开(公告)号：WO2006030373A1
公开(公告)日：2006-03-23
申请号：PCT/IB2005/052989
申请日：2005-09-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PUTZEYS, Bruno, J., G.
发明人： PUTZEYS, Bruno, J., G.
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： The present invention provides for a pulse width modulated noise shaper comprising an input adder having a first input for receiving an input signal and a second input, an output terminal, a filter with a substantially integrating characteristic having an input coupled to receive an output signal from said input adder, a pulse width modulation circuit having an input coupled to receive a signal derived from an output of the filter, an output coupled to the said output terminal, a control loop coupled to receive a signal derived from an output of said filter and to the second input of the adder, the control loop being arranged for generating a feedback signal representative of information conveyed by variable edges of a pulse width modulation signal and for feeding this feedback signal back to the second input of the adder.
摘要翻译：本发明提供了一种脉冲宽度调制的噪声整形器，包括具有用于接收输入信号的第一输入端和第二输入端的输入加法器，输出端子，具有基本上积分特性的滤波器，该滤波器具有耦合以接收来自所述输入加法器，具有耦合以接收从所述滤波器的输出导出的信号的输入的脉冲宽度调制电路，耦合到所述输出端子的输出端，耦合以接收从所述滤波器的输出导出的信号的控制环路;以及控制回路被布置用于产生表示由脉冲宽度调制信号的可变边缘传送的信息的反馈信号，并将该反馈信号送回加法器的第二输入端。

4. 发明申请

WO2006111932A1 INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND INTEGRATED CIRCUIT CONTROL METHOD 审中-公开
标题翻译：集成电路，电子设备和集成电路控制方法
公开(公告)号：WO2006111932A1
公开(公告)日：2006-10-26
申请号：PCT/IB2006/051219
申请日：2006-04-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VEENDRICK, Hendricus, J., M. , KATOCH, Atul
发明人： VEENDRICK, Hendricus, J., M. , KATOCH, Atul
IPC分类号： H03K19/00
CPC分类号： H03K19/0019
摘要： An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101; 102) from an active mode to a standby mode. The IC (10) comprises a further switch (141) having a first terminal coupled to a node (121) of the first conductive path between the first switch (131 ) and the first functional block (101) and a second terminal coupled to a node (122) of the second conductive path between the second switch (132) and the second functional block (102). The further switch (141) has a control terminal responsive to an enable signal indicating that the first switch (131) and the second switch (132) are disabled, thus allowing the recycling of charge between the first functional block (101) and the second functional block (102).
摘要翻译：集成电路（10）包括多个功能块（101,102,103），每个功能块（101,102,103）被耦合在第一电源线（110）和第二电源线（ 120）。第一功能块（101）经由包括第一开关（131）的第一导电路径耦合到第一电源线（110），并且第二功能块（102）经由第一电源线（110）经由包括第二开关（132）的第二导电路径，所述第一开关（131）和所述第二开关（132）被布置成分别将所述第一功能块（101）和所述第二功能块（102）与所述第一电源线路（110），用于将所述功能块（101; 102）从活动模式切换到待机模式。 IC（10）包括另外的开关（141），其具有耦合到第一开关（131）和第一功能块（101）之间的第一导电路径的节点（121）的第一端子和耦合到第一端子在第二开关（132）和第二功能块（102）之间的第二导电路径的节点（122）。另外的开关（141）具有响应于指示第一开关（131）和第二开关（132）被禁用的使能信号的控制端子，从而允许在第一功能块（101）和第二开关功能块（102）。

5. 发明申请

WO2006027739A2 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2006027739A2
公开(公告)日：2006-03-16
申请号：PCT/IB2005/052899
申请日：2005-09-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEAKE, Steven, T.
发明人： PEAKE, Steven, T.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/66712 , H01L29/7813
摘要： A method of manufacturing a semiconductor device comprising source and drain regions (13, 14, 14a) of a first conductivity type, and a channelaccommodating region (15) of a second, opposite conductivity type which separates the source and drain regions. The device comprises a gate (11, 42) which extends adjacent to the channel-accommodating region. The method includes the steps of etching a trench (27) into the semiconductor body of the device at a location laterally spaced from that of the gate (11, 42); and implanting a second conductivity type dopant into the body through the bottom (27b) of the trench to form a second conductivity type localised region (37) in the drain region. The dimensions and doping level of the localised level of the localised region (37) in the finished device is such that the localised region and adjacent portions of the drain region provide a voltage-sustaining spacecharge zone when depleted. This serves to substantially improve the trade-off between on-resistance and breakdown voltage in the resulting device in a cost effective manner.
摘要翻译：一种制造半导体器件的方法，该半导体器件包括第一导电类型的源极和漏极区域（13,14,14a），以及分隔源极和漏极区域的第二相反导电类型的沟道容纳区域（15）。该装置包括邻近通道容纳区延伸的门（11,42）。该方法包括以下步骤：在与栅极（11,42）的横向间隔开的位置处将沟槽（27）蚀刻到器件的半导体本体中; 以及通过所述沟槽的底部（27b）将第二导电类型的掺杂剂注入到所述主体中，以在所述漏极区域中形成第二导电类型的定位区域（37）。成品装置中的局部区域（37）的局部化水平的尺寸和掺杂水平使得漏极区域的局部区域和相邻部分在耗尽时提供电压维持空间充电区。这用于以成本有效的方式大大改善所得器件中的导通电阻和击穿电压之间的折衷。

6. 发明申请

WO2006131890A2 A CONTROL DEVICE FOR CONTROLLING THE OUTPUT OF ONE OR MORE FULL-BRIDGES 审中-公开
标题翻译：用于控制一个或多个全桥的输出的控制装置
公开(公告)号：WO2006131890A2
公开(公告)日：2006-12-14
申请号：PCT/IB2006/051813
申请日：2006-06-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , WILLAERT, Jurgen, M., A. , VAN DEN BERG, Arjan , BONGERS, Jozef, M., G.
发明人： WILLAERT, Jurgen, M., A. , VAN DEN BERG, Arjan , BONGERS, Jozef, M., G.
IPC分类号： H05B41/282
CPC分类号： H05B41/2825 , H05B41/2828
摘要： A control device (701 ) for controlling the output of one or more full- bridges (101 , 102) is described. The control device (701 ) reduces the amount of electromagnetic emissions by staggering the switching the outputs from the full-bridge inverters (101 , 102). This is achieved by synchronising the outputs to be symmetrical about a synchronisation pulse (305).
摘要翻译：描述了用于控制一个或多个全桥（101,102）的输出的控制装置（701）。控制装置（701）通过交错来自全桥逆变器（101,102）的输出来减少电磁发射量。这通过使关于同步脉冲（305）对称的输出同步来实现。

7. 发明申请

WO2006120640A2 FEEDBACK COMMUNICATION TECHNIQUE FOR SWITCHED MODE POWER SUPPLY 审中-公开
标题翻译：用于开关电源的反馈通信技术
公开(公告)号：WO2006120640A2
公开(公告)日：2006-11-16
申请号：PCT/IB2006/051452
申请日：2006-05-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHETTERS, Cornelis, J., A.
发明人： SCHETTERS, Cornelis, J., A.
CPC分类号： H02M3/33523 , H02M2001/0032 , Y02B70/16
摘要： A power conversion circuit for a switched mode power supply (SMPS) 11 is arranged to be switchable between a normal mode of operation and a burst standby mode of operation. In an embodiment, the SMPS 11 comprises an AC/DC stage having a primary (input) side and a secondary (output) side of a transformer 12. A switched mode power stage has a controller 15 on the primary side for controlling the switching of power to the secondary side. The controller 15 has a control input 3 for receiving feedback signals from a feedback circuit 50 on the secondary side of the transformer 12. The SMPS 11 comprises an opto coupler 20 arranged to communicate to the control input 3 of the controller 15 a feedback signal which indicates the start and the end of a switching cycle in the burst mode . Advantageously, this allows the SMPS 11 to react quicker to loads applied when in the burst standby mode.
摘要翻译：用于开关式电源（SMPS）11的电力转换电路被设置为可在正常操作模式和突发待机操作模式之间切换。在一个实施例中，SMPS 11包括具有变压器12的初级（输入）侧和次级（输出）侧的AC / DC级。开关模式功率级在初级侧具有控制器15，用于控制电源到二次侧。控制器15具有用于从变压器12的次级侧上的反馈电路50接收反馈信号的控制输入3.SMPS 11包括光耦合器20，光耦合器20布置成与控制器15的控制输入端3通信，反馈信号表示突发模式下开关周期的开始和结束。有利地，这允许SMPS 11对于在突发待机模式下施加的负载更快地做出反应。

8. 发明申请

WO2006129275A1 CIRCUIT AND METHOD FOR DETERMINING CURRENT IN A LOAD 审中-公开
标题翻译：用于确定负载中的电流的电路和方法
公开(公告)号：WO2006129275A1
公开(公告)日：2006-12-07
申请号：PCT/IB2006/051721
申请日：2006-05-30
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HEPPENSTALL, Keith
发明人： HEPPENSTALL, Keith
IPC分类号： H03K17/082
CPC分类号： H03K17/0822 , G01R19/0092 , H03K2217/0027
摘要： A circuit (1) is described for determining the current (I load ) in a load (6), the circuit having a main transistor (2) and a sense transistor (3), each transistor having a main current path (4, 5) and a control terminal (9, 10), the main current paths each operably connected in parallel between the load and a ground terminal (7) and the control terminals being connected together. Means is provided for setting the voltage across the main current path (5) of the sense transistor (3) to a voltage level substantially equal to a predetermined portion of the voltage across the main current path (4) of the main transistor (3).
摘要翻译：描述了用于确定负载（6）中的电流（I SUB负载）的电路（1），该电路具有主晶体管（2）和感测晶体管（3），每个晶体管具有主电流路径（4,5）和控制端子（9,10），每个可操作地并联连接在负载和接地端子（7）之间的主电流路径，并且控制端子连接在一起。提供了用于将感测晶体管（3）的主电流路径（5）两端的电压设定为与主晶体管（3）的主电流路径（4）的电压的预定部分基本相等的电压电平的装置，。

9. 发明申请

WO2006109265A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2006109265A1
公开(公告)日：2006-10-19
申请号：PCT/IB2006/051137
申请日：2006-04-12
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SONSKY, Jan
发明人： SONSKY, Jan
IPC分类号： H01L21/762
CPC分类号： H01L29/7824 , H01L21/76264 , H01L29/0653
摘要： A semiconductor device is formed by forming a second trench 120 at the base of a first trench 18, depositing insulator 124 at the base of the second trench 120, and then etching cavities 26 laterally from the sidewalls of the second trench, but not the base which is protected by insulator 124. The invention may in particular be used to form semiconductor devices with cavities under the active components, or by filling the cavities to form silicon on insulator or silicon on conductor devices.
摘要翻译：半导体器件通过在第一沟槽18的底部形成第二沟槽120，在第二沟槽120的底部沉积绝缘体124，然后从第二沟槽的侧壁横向蚀刻腔26而不是基底其由绝缘体124保护。本发明可以特别地用于形成具有在有源部件下方的空腔的半导体器件，或者通过填充空腔以在导体器件上形成绝缘体上的硅或硅。

10. 发明申请

WO2006097896A1 MOSFET WITH TEMPERATURE SENSE FACILITY 审中-公开
标题翻译：具有温度感应功能的MOSFET
公开(公告)号：WO2006097896A1
公开(公告)日：2006-09-21
申请号：PCT/IB2006/050796
申请日：2006-03-14
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HEPPENSTALL, Keith , BROWN, Adam , KOH, Adrian , KENNEDY, Ian
发明人： HEPPENSTALL, Keith , BROWN, Adam , KOH, Adrian , KENNEDY, Ian
IPC分类号： H01L27/02
CPC分类号： G01K7/01 , H01L27/0248
摘要： A transistor (1) has a FET (2) and a temperature sensing diode (4) integrated within it. Gate drive circuit (12) is arranged to switch off FET (2) and in this case biasing circuit (14) drives a constant current through the diode (4). The voltage across the diode (4) is measured by voltage sensor (15) which provides a measure of the temperature of the FET.
摘要翻译：晶体管（1）具有集成在其内的FET（2）和温度感测二极管（4）。栅极驱动电路（12）被布置为关断FET（2），并且在这种情况下，偏置电路（14）驱动通过二极管（4）的恒定电流。二极管（4）上的电压由电压传感器（15）测量，该电压传感器提供了FET的温度测量。

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