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1. 发明申请

WO2020069427A1 PANORAMIC LIGHT FIELD CAPTURE, PROCESSING AND DISPLAY 审中-公开
公开(公告)号：WO2020069427A1
公开(公告)日：2020-04-02
申请号：PCT/US2019/053635
申请日：2019-09-27
申请人： APPLE INC.
发明人： MOLINA, Gabriel D. , MOTTA, Ricardo J. , VONDRAN JR., Gary L. , LELESCU, Dan , RICK, Tobias , MILLER, Brett
IPC分类号： G06T1/00 , G06T5/50 , G06T7/00
摘要： A light field panorama system in which a user holding a mobile device performs a gesture to capture images of a scene from different positions. Additional information, for example position and orientation information, may also be captured. The images and information may be processed to determine metadata including the relative positions of the images and depth information for the images. The images and metadata may be stored as a light field panorama. The light field panorama may be processed by a rendering engine to render different 3D views of the scene to allow a viewer to explore the scene from different positions and angles with six degrees of freedom. Using a rendering and viewing system such as a mobile device or head-mounted display, the viewer may see behind or over objects in the scene, zoom in or out on the scene, or view different parts of the scene.

2. 发明申请

WO2019199817A1 QUEUE IN A NETWORK SWITCH 审中-公开
公开(公告)号：WO2019199817A1
公开(公告)日：2019-10-17
申请号：PCT/US2019/026571
申请日：2019-04-09
申请人： ADVANCED MICRO DEVICES, INC.
发明人： SMITH, Alan Dodson , KALYANASUNDHARAM, Vydhyanathan , BROUSSARD, Bryan P. , DONLEY, Greggory D. , PATEL, Chintan S.
IPC分类号： H04L12/861
摘要： A computing system uses a memory for storing data, one or more clients for generating network traffic and a communication fabric with network switches. The network switches include centralized storage structures, rather than separate input and output storage structures. The network switches store particular metadata corresponding to received packets in a single, centralized collapsing queue where the age of the packets corresponds to a queue entry position. The payload data of the packets are stored in a separate memory, so the relatively large amount of data is not shifted during the lifetime of the packet in the network switch. The network switches select sparse queue entries in the collapsible queue, deallocate the selected queue entries, and shift remaining allocated queue entries toward a first end of the queue with a delay proportional to the radix of the network switches.

3. 发明申请

WO2019183097A2 SHARING SYSTEM ACCESS USING A MOBILE DEVICE 审中-公开
公开(公告)号：WO2019183097A2
公开(公告)日：2019-09-26
申请号：PCT/US2019/022975
申请日：2019-03-19
申请人： APPLE INC.
发明人： HARIHARAN, Sriram , SIERRA, Yannick L. , JACOBS, Frederic
IPC分类号： G07C9/00 , H04W12/08 , H04W12/04
摘要： Techniques are disclosed relating to using a device to gain access to another system. In some embodiments, a first mobile device performs a pairing operation with a control unit that controls access to a system, the pairing operation including the first mobile device establishing a first cryptographic key with the control unit. The first mobile device receives a request to enable a second mobile device to communicate with the control unit, and in response to receiving the request, the first mobile device generates a second cryptographic key from the first cryptographic key. The first mobile device provides the second cryptographic key to the second mobile device. The second mobile device is configured to send a beacon including a payload encrypted with the second cryptographic key, and the encrypted payload is usable to authenticate the second mobile device to the control unit.

4. 发明申请

WO2019032444A1 SCRAMBLING SEQUENCE DESIGN FOR MULTI-MODE BLOCK DISCRIMINATION ON DCI BLIND DETECTION 审中-公开
公开(公告)号：WO2019032444A1
公开(公告)日：2019-02-14
申请号：PCT/US2018/045355
申请日：2018-08-06
申请人： COHERENT LOGIX, INC.
发明人： SHELBY, Kevin A. , LIU, Feng , STARKS, David R. , EARNSHAW, Mark
IPC分类号： H04L1/18 , H04L1/00
摘要： Methods and devices are described for polar encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on control information blind detection and decoding. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a user equipment (UE)-specific identifier, a UE group identifier, or a base station identifier. Frozen bits of the polar code may be used to encode and transmit hybrid automatic repeat request (HARQ) acknowledgment messaging for early retransmission of unsuccessful downlink messages. A tiered process of UE identification may be employed to improve a balance between early termination of the decoding process and success of the UE identification process.

5. 发明申请

WO2019005867A1 INTERPOSITION 审中-公开
公开(公告)号：WO2019005867A1
公开(公告)日：2019-01-03
申请号：PCT/US2018/039596
申请日：2018-06-26
申请人： APPLE INC.
发明人： GUIDA, Gianluca , RISTOVSKI, Aleksandar , VAN DER VEEN, Peter H. , WOODTKE, Shawn R. , MCPOLIN, Stephen J.
IPC分类号： G06F11/36
CPC分类号： G06F11/362 , G06F11/36
摘要： In an embodiment, an operating system is defined in terms of a set of actors, each of which implements one or more capabilities built into the system. The actors may establish channels between them for communication of messages between the actors. Some actors may interpose between other actors. These other actors may, in some cases, interpose on channels used by the base actor. In some embodiments, some channels may be interposed while others may be monitored by the interposing actor but may still communicate directly with the underlying actor. Some channels may not be affected by the interposition (e.g. the channels may not be interposed or monitored), in an embodiment. Other examples of interposition may include debugging, simulation, and sandboxing.

6. 发明申请

WO2017222576A1 ASYNCHRONOUS FEEDBACK TRAINING 审中-公开
标题翻译：异步反馈训练
公开(公告)号：WO2017222576A1
公开(公告)日：2017-12-28
申请号：PCT/US2016/050591
申请日：2016-09-08
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： LACKEY, Stanley, Ames, Jr. , TOHIDI, Damon , TALBOT, Gerald, R. , PRETE, Edoardo
IPC分类号： G06F13/16 , G06F5/06
CPC分类号： H04L1/0002 , H04L1/0073 , H04L1/244 , H04L7/0037 , H04L7/043 , H04L7/10 , H04L25/14 , H04L2012/5681
摘要： Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of 'N' clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.
摘要翻译：描述了用于实现异步反馈训练序列的系统，装置和方法。发射机经由包括多条数据线的通信信道向接收机发送训练序列指示。训练序列指示包括指示训练序列开始的比特序列。该指示包括在'N'个时钟周期长度的超循环的中点处从零到一个的转变，随后是预定数量的1。训练序列指示之后是测试模式。测试模式的开始发生在超级循环的末尾。接收机确定接收到的测试码型是否有错误，然后向发射机发送反馈，指出是否检测到任何错误。响应于接收到反馈，发射机改变一个或多个数据线的延迟设置。

7. 发明申请

WO2017040135A1 LAYER-LAYER REGISTRATION COUPON FOR PRINTED CIRCUIT BOARDS 审中-公开
标题翻译：印刷电路板层层注册机构
公开(公告)号：WO2017040135A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/048338
申请日：2016-08-24
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： MORAN, Stephanie , FREDA, Michael, C. , SAUTER, Karl
IPC分类号： H05K3/46 , H05K3/00 , H05K1/02 , H05K1/16
CPC分类号： G01R31/2813 , H05K1/0266 , H05K1/0268 , H05K1/0298 , H05K1/11 , H05K1/167 , H05K3/0052 , H05K3/0097 , H05K3/4679 , H05K2201/09381 , H05K2201/09636 , H05K2201/097 , H05K2201/09781 , H05K2203/166
摘要： A method and apparatus for determining misregistration of internal layers of a PCB using resistance measurements is disclosed. In one embodiment, a method includes measuring a first resistance between a first center terminal and a first peripheral terminal of a first registration coupon on a printed circuit board (PCB) panel (10) including at least one PCB (15). The method further includes measuring a second resistance between the first center terminal and a second peripheral terminal of the first registration coupon, wherein the first and second peripheral terminals are associated with a first internal layer of the PCB. A difference between the first and second resistances is then calculated. Then, based on this difference, a determination is made of a distance of misregistration of the first internal layer, if any, along a first axis.
摘要翻译：公开了一种用于使用电阻测量来确定PCB内部不对准的方法和装置。在一个实施例中，一种方法包括测量包括至少一个PCB（15）的印刷电路板（PCB）面板（10）上的第一配准优惠券的第一中心端子和第一外围端子之间的第一电阻。该方法还包括测量第一注册优惠券的第一中心终端和第二外围终端之间的第二电阻，其中第一和第二外围终端与PCB的第一内部层相关联。然后计算第一和第二电阻之间的差。然后，基于该差异，确定沿着第一轴线的第一内层的配准距离（如果有的话）。

8. 发明申请

WO2017023420A1 METHOD FOR CHAINING MEDIA PROCESSING 审中-公开
标题翻译：用于链接媒体处理的方法
公开(公告)号：WO2017023420A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/036688
申请日：2016-06-09
申请人： APPLE INC.
发明人： MILLET, Timothy J. , GULATI, Manu , SPENCE, Arthur L. , SAUND, Gurjeet S. , ESSER, Robert P.
IPC分类号： G06F9/48
CPC分类号： G06T1/20 , G06F9/4893 , G06F9/52 , G06T1/60 , G09G5/001 , G09G5/363 , G09G2360/08 , Y02D10/24
摘要： An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.
摘要翻译：系统的实施例可以包括多个媒体单元，处理器和电路。每个媒体单元可以被配置为执行一个或多个命令来处理显示图像。处理器可以被配置为在队列中存储多个媒体处理命令。电路可以被配置为从队列检索第一媒体处理命令，并将第一媒体处理命令发送到第一媒体单元。电路还可以被配置为响应于从第一媒体单元接收到中断而从队列中检索第二媒体处理并将第二媒体处理命令发送到第二媒体单元。响应于接收到来自第一媒体单元的中断，电路可以将数据从第一媒体单元复制到第二媒体单元。

9. 发明申请

WO2016201431A1 NITRIC OXIDE GENERATOR COMBINED WITH PDE5 INHIBITORS 审中-公开
标题翻译：氮氧化物发生器与PDE5抑制剂组合
公开(公告)号：WO2016201431A1
公开(公告)日：2016-12-15
申请号：PCT/US2016/037227
申请日：2016-06-13
申请人： AUSTECH PHARMACEUTICAL, LLC
发明人： BRYAN, Nathan Scott
IPC分类号： A61K31/519 , A61K31/495 , A61K36/00
CPC分类号： A61K33/00 , A61K9/0056 , A61K31/198 , A61K31/375 , A61K31/4985 , A61K31/519 , A61K31/714 , A61K36/21 , A61K36/28 , A61K36/734 , A61K45/06 , A61K2300/00
摘要： Described herein are compounds and methods of using nitric oxide (NO) generating compositions with a phosphodiesterase inhibitor of a phosphodiesterase that hydrolyzes cyclic guanosine monophosphate (cGMP) to improve the efficacy and decrease the side effects of these inhibitors.
摘要翻译：本文描述了使用一氧化氮（NO）产生组合物与磷酸二酯酶的磷酸二酯酶抑制剂水解环鸟嘌呤一磷酸（cGMP）以提高功效并降低这些抑制剂的副作用的化合物和方法。

10. 发明申请

WO2016160229A1 UNDER VOLTAGE DETECTION AND PERFORMANCE THROTTLING 审中-公开
标题翻译：在电压检测和性能曲线下
公开(公告)号：WO2016160229A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/020197
申请日：2016-03-01
申请人： APPLE INC.
发明人： TRIPATHI, Brijesh , SMITH, Eric G. , MACHNICKI, Erik P. , CHO, Jung Wook , ALASHMOUNY, Khaled M. , KATTEL, Kiran B. , BETTADA, Vijay M. , YANG, Bo , WEI, Wenlong
IPC分类号： G01R19/165 , G01R19/10 , G01R31/28 , G01R23/165
CPC分类号： G05F3/02 , G06F1/324 , G06F1/3296
摘要： An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.
摘要翻译：公开了一种欠压检测电路及其运算方法。在一个实施例中，IC包括欠压保护电路，其具有第一和第二比较器，其被配置为分别将电源电压与第一和第二电压阈值进行比较，其中第二电压阈值大于第一电压阈值。逻辑电路被耦合以从第一和第二比较器接收信号。在通过相应的功能电路在高性能状态下操作期间，逻辑电路被配置为响应于电源电压已经低于第一阈值的指示而导致节流信号的断言。提供给功能电路的时钟信号可以响应于指示而被节流。如果电源电压随后上升到高于第二阈值的水平，则节流信号可以被取消断言。

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