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1. 发明申请

WO2022256729A1 HORIZONTAL CENTERING OF SAMPLING POINT USING VERTICAL VERNIER 审中-公开
公开(公告)号：WO2022256729A1
公开(公告)日：2022-12-08
申请号：PCT/US2022/032287
申请日：2022-06-05
申请人： KANDOU LABS SA , KANDOU US, INC.
发明人： HORMATI, Ali , DEDIC, Peter
IPC分类号： H04L25/03 , H04L7/033 , H04L25/49
摘要： Methods and systems are described for measuring a vertical opening of a signal eye of a pulse amplitude modulated (PAM) signal received over a channel to determine a vertically-centered voltage decision threshold of a sampler receiving a sampling clock, determining channel-characteristic parameters indicative of a frequency response of the channel, determining a correctional vernier value from the channel-characteristic parameters, and generating a horizontally-centered voltage decision threshold that introduces a horizontal sampling offset in the sampling clock in a direction closer to a horizontal center of the signal eye by combining the vertically-centered voltage decision threshold and the correctional vernier value.

2. 发明申请

WO2022232474A1 REFERENCE GENERATION CIRCUIT FOR MAINTAINING TEMPERATURE-TRACKED LINEARITY IN AMPLIFIER WITH ADJUSTABLE HIGH-FREQUENCY GAIN 审中-公开
公开(公告)号：WO2022232474A1
公开(公告)日：2022-11-03
申请号：PCT/US2022/026882
申请日：2022-04-29
申请人： KANDOU LABS SA , KANDOU US, INC.
发明人： RATTAN, Suhas
IPC分类号： H03F3/191 , H03F3/193 , H03F3/45
摘要： Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.

3. 发明申请

WO2022212734A1 CLOCK AND DATA RECOVERY LOCK DETECTION CIRCUIT FOR VERIFYING LOCK CONDITION IN PRESENCE OF IMBALANCED EARLY TO LATE VOTE RATIOS 审中-公开
公开(公告)号：WO2022212734A1
公开(公告)日：2022-10-06
申请号：PCT/US2022/022873
申请日：2022-03-31
申请人： KANDOU LABS SA , KANDOU US, INC.
发明人： GHARIBDOUST, Kiarash , HORMATI, Ali
IPC分类号： H04L7/00 , H04L7/033 , H03L7/10 , H03K19/21 , H03L7/0807 , H03L7/0891 , H03L7/197 , H04L7/0004 , H04L7/0025
摘要： Methods and systems are described for generating early and late votes for a clock recovery system, each early or late vote associated with a detected transitional data pattern in a data stream, generating a first early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a first time interval, generating a second early-late vote measurement reflective of an imbalance between the early and late votes that are generated during a second time interval, comparing the first and the second early-late vote measurements, and outputting a CDR-lock signal at least in part responsive to determining that the first and the second early-late vote measurements are within a predetermined threshold.

4. 发明申请

WO2020055888A1 PROGRAMMABLE CONTINUOUS TIME LINEAR EQUALIZER HAVING STABILIZED HIGH-FREQUENCY PEAKING FOR CONTROLLING OPERATING CURRENT OF A SLICER 审中-公开
公开(公告)号：WO2020055888A1
公开(公告)日：2020-03-19
申请号：PCT/US2019/050440
申请日：2019-09-10
申请人： KANDOU LABS, S.A. , KANDOU US, INC.
发明人： TAJALLI, Armin , WALTER, Christoph
IPC分类号： H03F1/30 , H03F3/187 , H03F3/45 , H04L25/00
摘要： Methods and systems are described that include a differential amplifier driving an active load circuit, the active load circuit having a pair of load transistors and a high-frequency gain stage providing high frequency peaking for the active load circuit according to a frequency response characteristic determined in part by resistive values of a pair of active resistors connected, respectively, to gates of the pair of load transistors, and a bias circuit configured to stabilize the high frequency peaking of the high-frequency gain stage by generating a process-and-temperature variation (PVT)-dependent control voltage at gates of the active resistors to stabilize the resistive values of the pair of active resistors to account for PVT-dependent voltages at the gates of the pair of load transistors.

5. 发明申请

WO2019241081A1 PASSIVE MULTI-INPUT COMPARATOR FOR ORTHOGONAL CODES ON A MULTI-WIRE BUS 审中-公开
公开(公告)号：WO2019241081A1
公开(公告)日：2019-12-19
申请号：PCT/US2019/036170
申请日：2019-06-07
申请人： KANDOU LABS, S.A. , KANDOU US, INC.
发明人： TAJALLI, Armin , CAO, Chen , GHARIBDOUST, Kiarash
IPC分类号： H04L25/02 , H04L25/49 , H03M7/20 , H04B3/02 , H04L1/00 , H04L25/08
摘要： Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

6. 发明申请

WO2019241080A1 SKEW DETECTION AND CORRECTION FOR ORTHOGONAL DIFFERENTIAL VECTOR SIGNALING CODES 审中-公开
公开(公告)号：WO2019241080A1
公开(公告)日：2019-12-19
申请号：PCT/US2019/036169
申请日：2019-06-07
申请人： KANDOU LABS, S.A. , KANDOU US, INC.
发明人： HORMATI, Ali
IPC分类号： H04L25/02 , H04L7/00 , H04L25/49 , H03M7/20 , H04B3/02 , H04L1/00 , H04L25/08 , H04L25/14
摘要： Methods and systems are described for receiving a plurality of signals corresponding to symbols of a codeword on a plurality of wires of a multi-wire bus, and responsively generating a plurality of sub-channel outputs using a plurality of multi-input comparators (MICs) connected to the plurality of wires of the multi-wire bus, generating a plurality of wire-specific skew control signals, each wire-specific skew control signal of the plurality of wire-specific skew control signals generated by combining (i) one or more sub-channel specific skew measurement signals associated with corresponding sub-channel outputs undergoing a transition and (ii) a corresponding wire-specific transition delta, and providing the plurality of wire-specific skew control signals to respective wire-skew control elements to adjust wire-specific skew.

7. 发明申请

WO2019113549A1 DECISION FEEDBACK EQUALIZATION CORRECTION OF EYE SCOPE MEASUREMENTS 审中-公开
公开(公告)号：WO2019113549A1
公开(公告)日：2019-06-13
申请号：PCT/US2018/064619
申请日：2018-12-07
申请人： KANDOU LABS, S.A. , KANDOU US, INC.
发明人： SIMPSON, Richard
IPC分类号： H04B3/466 , H04L25/03 , H04L25/06 , G06F11/32
摘要： Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.

8. 发明申请

WO2018200315A1 METHOD AND APPARATUS FOR PROJECTING COLLISION-DETERRENTS IN VIRTUAL REALITY VIEWING ENVIRONMENTS 审中-公开
公开(公告)号：WO2018200315A1
公开(公告)日：2018-11-01
申请号：PCT/US2018/028451
申请日：2018-04-19
申请人： PCMS HOLDINGS, INC.
发明人： HWANG, Sungjae , GIM, Junghyeon
IPC分类号： G06F3/01 , G02B27/01
CPC分类号： G06F3/011 , G02B27/017 , G02B2027/0138 , G02B2027/014 , G02B2027/0141 , G02B2027/0187
摘要： Some embodiments of methods and systems disclosed herein include displaying, in a virtual space, a virtual reality (VR) content to a user of a head-mounted display (HMD) device; determining a probable-collision frame representing a region with a probability of entry by the user; and projecting, on a surface proximate to the user, an indication of the probable-collision frame.

9. 发明申请

WO2018191749A1 PIPELINED FORWARD ERROR CORRECTION FOR VECTOR SIGNALING CODE CHANNEL 审中-公开
公开(公告)号：WO2018191749A1
公开(公告)日：2018-10-18
申请号：PCT/US2018/027791
申请日：2018-04-16
申请人： KANDOU LABS, S.A. , INVENTION MINE, LLC
发明人： SHOKROLLAHI, Amin , CARNELLI, Dario
IPC分类号： H04B3/02 , H04B17/364 , H04L1/00 , H04L25/03 , H04L25/08
摘要： Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

10. 发明申请

WO2017096264A1 WIDEBAND POLAR RECEIVER ARCHITECTURE AND SIGNAL PROCESSING METHODS 审中-公开
标题翻译：宽带极化接收机体系结构和信号处理方法
公开(公告)号：WO2017096264A1
公开(公告)日：2017-06-08
申请号：PCT/US2016/064772
申请日：2016-12-02
申请人： INNOPHASE INC.
发明人： XU, Yang , HERMOSO, Sara Munoz , PEREZ, Roc Berenguer
IPC分类号： H04L27/04 , H03C1/52
CPC分类号： H04L27/389 , H03D3/007 , H03D2200/006
摘要： Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.
摘要翻译：描述了宽带极坐标接收机和操作方法。相位调制输入信号在包括注入锁定振荡器的极性接收器处被接收。注入锁定振荡器包括多个注入点。基于输入信号的频率，选择特定的N次谐波，并且输入信号在对应于所选N次谐波的一组注入点处被注入。注入锁定振荡器产生振荡器输出信号，并且从振荡器输出信号的相位确定输入信号的相位。在一些实施例中，振荡器输出信号被倍频N，与输入信号混合并被滤波用于幅度检测。输入信号根据相位和幅度信息进行解码。

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