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1. 发明授权

US07813211B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07813211B2
公开(公告)日：2010-10-12
申请号：US11956822
申请日：2007-12-14
申请人： Kyung-Whan Kim , Seok-Cheol Yoon
发明人： Kyung-Whan Kim , Seok-Cheol Yoon
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C7/1078 , G11C7/1093 , G11C7/1096 , G11C11/4076 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory device having read and write operations includes a discrimination signal generating unit for generating a discrimination signal during the write operation; and a selective delay unit for receiving and selectively delaying a command-group signal in response to the discrimination signal.
摘要翻译：具有读和写操作的半导体存储器件包括：识别信号产生单元，用于在写操作期间产生鉴别信号; 以及选择延迟单元，用于响应于所述鉴别信号接收和选择性地延迟命令组信号。

2. 发明授权

US07811929B2 Method for forming dual damascene pattern 有权
标题翻译：形成双镶嵌图案的方法
公开(公告)号：US07811929B2
公开(公告)日：2010-10-12
申请号：US11812910
申请日：2007-06-22
申请人： Ki Lyoung Lee , Jung Gun Heo
发明人： Ki Lyoung Lee , Jung Gun Heo
IPC分类号： H01L21/768
CPC分类号： H01L21/76808 , G03F7/091 , H01L21/0276 , H01L21/31144
摘要： A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film.
摘要翻译：形成双镶嵌图案的方法包括制备包括硅树脂作为基础树脂的多功能硬掩模组合物; 在硬接线层上形成包括自配置接触绝缘膜，第一电介质膜，蚀刻阻挡膜和第二电介质膜的沉积结构; 蚀刻沉积结构以暴露硬接线层，从而形成通孔; 在第二电介质膜和通孔中形成多功能硬掩模组合物以形成多功能硬掩模膜; 并蚀刻所得到的结构以暴露第一电介质膜的一部分，从而形成宽度大于通孔的宽度的沟槽; 并去除多功能硬掩模膜。

3. 发明授权

US07800962B2 Bit line control circuit for semiconductor memory device 有权
标题翻译：半导体存储器件的位线控制电路
公开(公告)号：US07800962B2
公开(公告)日：2010-09-21
申请号：US12187841
申请日：2008-08-07
申请人： Khil-Ohk Kang
发明人： Khil-Ohk Kang
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C7/06 , G11C7/12 , G11C11/4074 , G11C11/4091
摘要： A semiconductor memory device includes a bit line sense amplifier for sensing and amplifying data applied on a bit line; a first driver for driving a pull-up voltage line of the bit line sense amplifier to a voltage applied on a normal driving voltage terminal; an overdriving signal generator for generating an overdriving signal defining an overdriving period in response to an active command; an overdriving control signal generator for receiving the overdriving signal to generate an overdriving control signal for selectively performing an overdriving operation according to a voltage level of an overdriving voltage; and a second driver for driving the normal driving voltage terminal to the overdriving voltage in response to the overdriving control signal.
摘要翻译：一种半导体存储器件包括用于感测和放大施加在位线上的数据的位线读出放大器; 用于将位线读出放大器的上拉电压线驱动到施加在正常驱动电压端子上的电压的第一驱动器; 过驱动信号发生器，用于产生响应于有效命令定义过驱动周期的过驱动信号; 过驱动控制信号发生器，用于接收过驱动信号以产生过驱动控制信号，用于根据过驱动电压的电压电平选择性地执行过驱动; 以及用于响应于过驱动控制信号将正常驱动电压端驱动到过驱动电压的第二驱动器。

4. 发明授权

US07791945B2 Semiconductor memory device including apparatus for detecting threshold voltage 失效
标题翻译：半导体存储器件包括用于检测阈值电压的装置
公开(公告)号：US07791945B2
公开(公告)日：2010-09-07
申请号：US12003675
申请日：2007-12-31
申请人： Yoon-Jae Shin , Jun-Gi Choi
发明人： Yoon-Jae Shin , Jun-Gi Choi
IPC分类号： G11C11/34
CPC分类号： G11C11/4074 , G11C5/145
摘要： A semiconductor device including a threshold voltage detector and a boosted voltage generating unit. The threshold voltage detector detects a threshold voltage level of cell transistors and outputs a detected threshold voltage level. The boosted voltage generating unit changes a target level of a boosted voltage in response to the detected threshold voltage level. The threshold voltage detector includes a detected current generating unit and a detected voltage generating unit. The detected current generating unit has a plurality of cell transistors in a cell array and generates a detected current whose amplitude varies corresponding to an average level of the threshold voltages of the cell transistors. The detected voltage generating unit generates the detected threshold voltage level whose level is determined corresponding to the amplitude of the detected current.
摘要翻译：一种包括阈值电压检测器和升压电压产生单元的半导体器件。阈值电压检测器检测单元晶体管的阈值电压电平，并输出检测到的阈值电压电平。升压电压发生单元响应于检测到的阈值电压电平而改变升压电压的目标电平。阈值电压检测器包括检测电流产生单元和检测电压产生单元。检测电流产生单元具有单元阵列中的多个单元晶体管，并产生其幅度根据单元晶体管的阈值电压的平均电平而变化的检测电流。检测电压产生单元产生检测到的阈值电压电平，其电平根据检测到的电流的幅度确定。

5. 发明授权

US07786791B2 Internal voltage generation circuit 有权
标题翻译：内部电压产生电路
公开(公告)号：US07786791B2
公开(公告)日：2010-08-31
申请号：US12130623
申请日：2008-05-30
申请人： Jae-Boum Park
发明人： Jae-Boum Park
IPC分类号： G05F1/10
CPC分类号： H02M1/088 , H02M3/07
摘要： Internal voltage generation circuit including a reference oscillation signal generator for generating a reference oscillation signal according to a comparison result of a pumping voltage with a reference voltage, an oscillation signal generator for generating a plurality of oscillation signals with a predetermined phase difference and a pumping voltage generator for generating a pumping voltage through sequential charge pumping operations performed in response to the plurality of oscillation signals, respectively.
摘要翻译：内部电压产生电路，包括用于根据具有参考电压的泵浦电压的比较结果产生参考振荡信号的参考振荡信号发生器，用于产生具有预定相位差的多个振荡信号的振荡信号发生器和泵浦电压发生器，用于通过分别响应于所述多个振荡信号执行的顺序电荷泵送操作产生泵浦电压。

6. 发明授权

US07782698B2 Refresh signal generator of semiconductor memory device 失效
标题翻译：半导体存储器件的刷新信号发生器
公开(公告)号：US07782698B2
公开(公告)日：2010-08-24
申请号：US11966838
申请日：2007-12-28
申请人： Tae-Kyun Kim
发明人： Tae-Kyun Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40626 , G11C2211/4061
摘要： A refresh signal generator generates an internal refresh signal to conduct a refresh with an interval controlled based on PVT fluctuations. The refresh signal generator includes a temperature sensing unit for sensing an internal temperature and activating a corresponding signal of a plurality of temperature sensing signals in response to a temperature sense driving signal, a power supply selecting unit for driving a driving voltage supply terminal to one of different voltage levels according to the plurality of temperature sensing signals, and an internal refresh signal generating unit for receiving a driving voltage from the power supply selecting unit and producing internal refresh signals at a constant interval.
摘要翻译：刷新信号发生器产生内部刷新信号，以基于PVT波动控制的间隔进行刷新。刷新信号发生器包括：温度检测单元，用于响应于温度感测驱动信号感测内部温度并激活多个温度感测信号的对应信号;电源选择单元，用于将驱动电压供应端驱动到根据多个温度感测信号的不同的电压电平，以及内部刷新信号生成单元，用于从电源选择单元接收驱动电压，并以恒定间隔产生内部刷新信号。

7. 发明授权

US07778095B2 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07778095B2
公开(公告)日：2010-08-17
申请号：US12000698
申请日：2007-12-17
申请人： Kwang-Jin Na
发明人： Kwang-Jin Na
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0814
摘要： A semiconductor memory device includes a delay locked loop (DLL) unit configured to generate a plurality of DLL clocks, each having a different phase according to delay values predefined by a DLL operation; a data output buffering unit configured to output data in response to the DLL clocks; and a skew compensating unit disposed between the DLL unit and the data output buffering unit to remove a clock skew occurring when the DLL clocks are transferred to the data output buffering unit.
摘要翻译：半导体存储器件包括延迟锁定环（DLL）单元，被配置为产生多个DLL时钟，每个DLL时钟根据由DLL操作预定义的延迟值具有不同的相位; 数据输出缓冲单元，被配置为响应于所述DLL时钟输出数据; 以及偏置补偿单元，设置在DLL单元和数据输出缓冲单元之间，以消除当DLL时钟被传送到数据输出缓冲单元时发生的时钟偏移。

8. 发明授权

US07773448B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07773448B2
公开(公告)日：2010-08-10
申请号：US12136487
申请日：2008-06-10
申请人： Dae-Suk Kim , Jin-Hee Cho
发明人： Dae-Suk Kim , Jin-Hee Cho
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C8/12 , G11C8/18
摘要： A semiconductor memory device having multiple banks each including multiple memory blocks arranged in column and row directions. The memory blocks are divided into multiple memory block groups each sharing a corresponding column select signal. The memory blocks belonging to the respective memory block groups are arranged adjacently in the column direction. Multiple global input/output lines are separately connected to the memory block groups of the respective banks to transfer data of the memory blocks belonging to the respective memory block groups in a time division manner.
摘要翻译：一种具有多个存储体的半导体存储器件，每个存储体包括以列和行方向布置的多个存储块。存储器块被分成多个存储器块组，每个存储块组共享相应的列选择信号。属于相应存储块组的存储器块在列方向上相邻布置。多个全局输入/输出线分别连接到各个存储体的存储器块组，以时分方式传送属于各个存储块组的存储块的数据。

9. 发明授权

US07768327B2 Delay locked loop of semiconductor device and method for driving the same 有权
标题翻译：半导体器件的延迟锁定环路及其驱动方法
公开(公告)号：US07768327B2
公开(公告)日：2010-08-03
申请号：US11819818
申请日：2007-06-29
申请人： Hye-Young Lee
发明人： Hye-Young Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0812
摘要： A delay locked loop (DLL) of a semiconductor device includes: a first delay line for delaying a first clock signal in synchronization with a first edge of an external clock signal to output a first delayed clock signal; a second delay line for delaying a second clock signal in synchronization with a second edge of the external clock to output a second delayed clock signal; a duty cycle corrector (DCC) for mixing phases of the first and second delayed clock signals to output a DLL clock signal with a corrected duty cycle; and a DCC controller for disabling the duty cycle corrector in a section during which a phase difference between the first and second delayed clock signals is greater than a preset time after a delay locking.
摘要翻译：半导体器件的延迟锁定环（DLL）包括：第一延迟线，用于与第一外部时钟信号的第一边沿同步地延迟第一时钟信号，以输出第一延迟的时钟信号; 第二延迟线，用于与所述外部时钟的第二边沿同步地延迟第二时钟信号，以输出第二延迟时钟信号; 用于混合第一和第二延迟时钟信号的相位的占空比校正器（DCC），以输出具有校正占空比的DLL时钟信号; 以及DCC控制器，用于在第一和第二延迟时钟信号之间的相位差大于延迟锁定之后的预设时间的部分中禁用占空比校正器。

10. 发明授权

US07755390B2 XOR logic circuit 有权
公开(公告)号：US07755390B2
公开(公告)日：2010-07-13
申请号：US12345751
申请日：2008-12-30
申请人： Jin-Yeong Moon
发明人： Jin-Yeong Moon
IPC分类号： G06F7/50 , H03K19/21
摘要： An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.

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