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1. 发明申请

WO2019168523A1 VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2019168523A1
公开(公告)日：2019-09-06
申请号：PCT/US2018/020204
申请日：2018-02-28
申请人： INTEL CORPORATION
发明人： HUANG, Cheng-Ying , KAVALIEROS, Jack , YOUNG, Ian , METZ, Matthew , RACHMADY, Willy , AVCI, Uygar , AGRAWAL, Ashish , CHU-KUNG, Benjamin
IPC分类号： H01L29/73 , H01L29/732 , H01L29/66 , H01L29/78
摘要： Tunneling Field Effect Transistors (TFETs) can offer significant performance increases and energy consumption decreases relative to traditional metal oxide semiconductor (MOS) transistors due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In another embodiment, the channel can include a gradient layer. In an embodiment, the channel can include an indium(x) gallium(l-x) arsenide (InxGai-xAs) layer. In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates.

2. 发明申请

WO2019168522A1 VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2019168522A1
公开(公告)日：2019-09-06
申请号：PCT/US2018/020200
申请日：2018-02-28
申请人： INTEL CORPORATION
发明人： HUANG, Cheng-Ying , KAVALIEROS, Jack , YOUNG, Ian , METZ, Matthew , RACHMADY, Willy , AVCI, Uygar , AGRAWAL, Ashish , CHU-KUNG, Benjamin
IPC分类号： H01L29/73 , H01L29/732 , H01L29/772 , H01L29/423 , H01L29/66
摘要： Tunneling Field Effect Transistors (TFETs) can offer significant performance increases and energy consumption decreases relative to traditional metal oxide semiconductor (MOS) transistors due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, silicon, germanium, III-V semiconductors, gallium nitride, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be substantially perpendicular to the substrate.

3. 发明申请

WO2019132995A1 SELECTORS FOR MEMORY DEVICES 审中-公开
公开(公告)号：WO2019132995A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/069092
申请日：2017-12-29
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , KARPOV, Elijah V. , MAJHI, Prashant , SHARMA, Abhishek A. , DOYLE, Brian S.
IPC分类号： H01L45/00 , H01L43/02
摘要： Disclosed herein are systems, methods, and apparatuses that are directed to a selector for use in connection with memory devices. In an embodiment, the selector can comprise a device that has current-voltage characteristics that are symmetric under opposing voltage biases. In an embodiment, the selector can be used in connection with a portion of a memory array, for example, in connection with wordlines and bitlines used in the memory array. In an embodiment, the selector can turn a memory device, for example, an resistive memory device such as an spin-transfer torque memory (STTM) device, on or off.

4. 发明申请

WO2019125392A1 INTEGRATED CIRCUIT STRUCTURES, SELECTOR DEVICES, AND METHODS 审中-公开
公开(公告)号：WO2019125392A1
公开(公告)日：2019-06-27
申请号：PCT/US2017/067127
申请日：2017-12-18
申请人： INTEL CORPORATION
发明人： KOTLYAR, Roza , PILLARISETTY, Ravi , KARPOV, Elijah , DOYLE, Brian , SHARMA, Abhishek
IPC分类号： H01L45/00
摘要： Integrated circuit structures are provided that may include a first insulating-to-metallic transition material, a second insulating-to-metallic transition material, and a third layer. The third layer may have an electron affinity that is greater than the electron affinity of at least one of the first insulating-to-metallic transition material or the second insulating-to-metallic transition material. Selectors that include integrated circuit structures also are provided.

5. 发明申请

WO2019139621A1 TRANSISTORS INCLUDING FIRST AND SECOND SEMICONDUCTOR MATERIALS BETWEEN SOURCE AND DRAIN REGIONS AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2019139621A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/013602
申请日：2018-01-12
申请人： INTEL CORPORATION
发明人： DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , THEN, Han Wui
IPC分类号： H01L29/417 , H01L21/8234 , H01L29/66
摘要： Methods, apparatus, systems and articles of manufacture are disclosed for transistors including first and second semiconductor materials between source and drain regions. An example apparatus includes a transistor comprising a first semiconductor material including gallium and nitrogen and a second semiconductor material including gallium and oxygen, where the second semiconductor material is adjacent the first semiconductor material. The disclosed example apparatus further includes a source proximate the first semiconductor material and spaced apart from the second semiconductor material and a drain proximate the second semiconductor material and spaced apart from the first semiconductor material. The disclosed example apparatus also includes a gate located between the source and the drain.

6. 发明申请

WO2019168521A1 VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2019168521A1
公开(公告)日：2019-09-06
申请号：PCT/US2018/020195
申请日：2018-02-28
申请人： INTEL CORPORATION
发明人： HUANG, Cheng-Ying , KAVALIEROS, Jack , YOUNG, Ian , METZ, Matthew , RACHMADY, Willy , AVCI, Uygar , AGRAWAL, Ashish , CHU-KUNG, Benjamin
IPC分类号： H01L29/73 , H01L29/732 , H01L29/66 , H01L29/423 , H01L29/417 , H01L21/8234 , H01L21/28
摘要： Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of later TFETs. In an embodiment, the disclosed vertical TFETs can have a drain that is deposited in a trench.

7. 发明申请

WO2013137930A1 DETERMINING THE POSITION OF A MOBILE DEVICE IN AN INDOOR ENVIRONMENT 审中-公开
标题翻译：确定移动设备在室内环境中的位置
公开(公告)号：WO2013137930A1
公开(公告)日：2013-09-19
申请号：PCT/US2012/053675
申请日：2012-09-04
申请人： EMPIRE TECHNOLOGY DEVELOPMENT LLC , KEERTHI, Arvind Vijay
发明人： KEERTHI, Arvind Vijay
IPC分类号： G01S5/02 , G01S5/00 , H04W64/00
CPC分类号： H04W4/04 , G01S5/0215 , H04L25/0212 , H04L25/0228 , H04L25/024 , H04L27/2613 , H04W4/02 , H04W64/00 , H04W88/02 , H04W88/08
摘要： Technologies and implementations for determining the location of device in an indoor environment are generally disclosed. The disclosed method comprises: receiving, via a mobile device, a wideband transmission transmitted from at least one base station, including distributed traffic symbol portions, distributed pilot symbol portions, and intermittent punctured pilot symbol portions; determining, via the mobile device, a first path portion of the wideband transmission based at least in part on the intermittent punctured pilot symbol portions, wherein the first path portion of the wideband transmission is associated with a first time delay; determining, via the mobile device, a distance between the mobile device and the at least one base station based at least in part on the first time delay; and determining, via the mobile device, a location of the mobile device based at least in part on the determined distance.
摘要翻译：通常公开了用于确定室内环境中的设备位置的技术和实施方式。所公开的方法包括：经由移动设备接收从至少一个基站发送的宽带传输，包括分布式业务符号部分，分布式导频符号部分和间歇性穿孔导频符号部分; 至少部分地基于间歇穿孔导频符号部分，经由移动设备确定宽带传输的第一路径部分，其中宽带传输的第一路径部分与第一时间延迟相关联; 经由所述移动设备至少部分地基于所述第一时间延迟来确定所述移动设备与所述至少一个基站之间的距离; 以及至少部分地基于所确定的距离，经由所述移动设备确定所述移动设备的位置。

8. 发明申请

WO2021002898A1 BATTERY CHARGING WITH LITHIUM PLATING DETECTION AND BATTERY DEGRADATION DETECTION AND SEPARATION 审中-公开
公开(公告)号：WO2021002898A1
公开(公告)日：2021-01-07
申请号：PCT/US2020/024479
申请日：2020-03-24
申请人： INTEL CORPORATION
发明人： MATSUMURA, Naoki , GORIUS, Aaron
IPC分类号： H02J7/00 , G01R31/3835 , G01R31/396 , G01R31/392 , G01R31/389
摘要： In some examples, an apparatus includes a controller to monitor voltage of a battery during constant current charging of the battery, and to detect lithium plating of the battery based on a rate of change of the monitored voltage of the battery during constant current charging of the battery. In some examples, a battery module includes a plurality of battery cells connected in parallel, and a controller to determine an impedance of each of the plurality of battery cells, and to disconnect one of the plurality of battery cells from the plurality of battery cells based on a relation of the impedance of the one of the plurality of battery cells with a threshold impedance.

9. 发明申请

WO2019139622A1 FERROELECTRIC FIELD-EFFECT TRANSISTORS FOR 3D MEMORY ARRAYS AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2019139622A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/013604
申请日：2018-01-12
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , KARPOV, Elijah, V. , DOYLE, Brian, S. , SHARMA, Abhishek, A. , PILLARISETTY, Ravi
IPC分类号： H01L27/11514 , H01L27/11507 , H01L27/11509 , H01L27/11512 , H01L21/28
摘要： Methods, apparatus, systems and articles of manufacture are disclosed for a gate all around ferroelectric material field-effect transistor. Examples include a ferroelectric memory device that includes a semiconductor substrate, a semiconductor rod extending in an elongate direction substantially parallel to the semiconductor substrate, a ferroelectric gate insulator coating the semiconductor rod and a gate conductor adjacent the semiconductor rod, the ferroelectric gate insulator positioned between the gate conductor and the semiconductor rod.

10. 发明申请

WO2019132996A1 FERROELECTRIC GATE DIELECTRICS IN INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2019132996A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/069093
申请日：2017-12-29
申请人： INTEL CORPORATION
发明人： SHARMA, Abhishek A. , DOYLE, Brian S. , MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V.
IPC分类号： H01L27/1159 , H01L27/11592 , H01L27/11595 , H01L21/28 , H01L29/51
摘要： In various embodiments disclosed herein are systems, methods, and apparatuses for using a ferroelectric material as a gate dielectric in an integrated circuit, for example, as part of a transistor. In an embodiment, the transistor can include a p-type metal oxide semiconductor (PMOS) transistor. In an embodiment, the transistor can have a p-doped substrate. In an embodiment, the channel of the transistor can be a p-doped channel. In an embodiment, the transistor having the ferroelectric material as the gate dielectric can be used in connection with an inverter. In an embodiment, the inverter can be used in connection with an static random access memory (SRAM) memory device.

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