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1. 发明申请

WO2013188059A1 COMMUNICATION SYSTEM AND METHOD FOR SYNCHRONIZING A PLURALITY OF NETWORK NODES AFTER A NETWORK LOCK CONDITION OCCURS 审中-公开
标题翻译：通信系统和方法用于在网络锁定状态下同步多个网络节点
公开(公告)号：WO2013188059A1
公开(公告)日：2013-12-19
申请号：PCT/US2013/041818
申请日：2013-06-12
申请人： MICROCHIP TECHNOLOGY INC.
发明人： AKKIHAL, Shivanand, I. , MUELLER, Rainer
IPC分类号： H04J3/06 , H04N21/43
CPC分类号： H04J3/0638 , H04J3/0647 , H04J3/0673
摘要： A communication system and method is provided herein for synchronizing a plurality of network nodes after a network lock condition occurs within a network. According to one embodiment, the method may generate a local trigger signal simultaneously at each of the plurality of network nodes by compensating for unique phase delays attributed to each of the plurality of network nodes. As described herein, the local trigger signals may be used for synchronizing devices, such as multimedia devices, which may be coupled to the network nodes. More specifically, the local trigger signals may be used to synchronize events occurring within devices, which are coupled to different nodes of the network.
摘要翻译：本文提供了一种在网络中发生网络锁定状况之后同步多个网络节点的通信系统和方法。根据一个实施例，该方法可以通过补偿归因于多个网络节点中的每一个的唯一相位延迟来在多个网络节点中的每一个处同时生成本地触发信号。如本文所述，本地触发信号可以用于同步诸如多媒体设备的设备，其可以耦合到网络节点。更具体地，本地触发信号可以用于同步在耦合到网络的不同节点的设备内发生的事件。

2. 发明申请

WO2013009537A1 LUMINANCE CONTROL FOR ILLUMINATION DEVICES 审中-公开
标题翻译：照明设备的照明控制
公开(公告)号：WO2013009537A1
公开(公告)日：2013-01-17
申请号：PCT/US2012/045392
申请日：2012-07-03
申请人： KETRA, INC. , KNAPP, David, J.
发明人： KNAPP, David, J.
IPC分类号： H05B33/08
CPC分类号： H05B33/0869
摘要： An illumination device is provided having one or more illumination LEDs configured to provide illumination for the device. Along with the illumination LED is a reference LED. The illumination LED provide illumination during normal operation of the device, whereas the reference LED provides a reference illumination, but does not provide illumination during normal operation. A light detector can detect light from the illumination LED and the reference LED, and control circuitry can be used to compare light detected from the reference LED and the illumination LED to adjust a brightness for the device. The light detector can comprise a photo-detector or can comprise an LED, such as one of the illumination LEDs if more than one illumination LED is utilized. A method is also provided for controlling brightness of an illumination device.
摘要翻译：提供了一种照明装置，其具有被配置为为装置提供照明的一个或多个照明LED。随着照明LED是一个参考LED。照明LED在设备的正常操作期间提供照明，而参考LED提供参考照明，但在正常操作期间不提供照明。光检测器可以检测来自照明LED和参考LED的光，并且可以使用控制电路来比较从参考LED和照明LED检测到的光，以调整器件的亮度。如果使用多于一个的照明LED，则光检测器可以包括光检测器或者可以包括LED，诸如照明LED中的一个。还提供了一种用于控制照明装置的亮度的方法。

3. 发明申请

WO2007081634A2 LOW POWER BANDGAP REFERENCE CIRCUIT WITH INCREASED ACCURACY AND REDUCED AREA CONSUMPTION 审中-公开
标题翻译：低功率带宽参考电路具有提高的精度和降低的面积消耗
公开(公告)号：WO2007081634A2
公开(公告)日：2007-07-19
申请号：PCT/US2006/061992
申请日：2006-12-13
申请人： CYPRESS SEMICONDUCTOR CORP. , GEORGESCU, Bogdan, I. , GRADINARIU, Iulian C.
发明人： GEORGESCU, Bogdan, I. , GRADINARIU, Iulian C.
IPC分类号： G05F3/30
CPC分类号： G05F3/30
摘要： Bandgap reference (BGR) circuits and methods are described herein for providing high accuracy, low power Bandgap operation when using small, low voltage devices in the analog blocks of the BGR circuit. In some cases, chopped input stabilization and dynamic current matching techniques may be combined to compensate for input voltage offsets in the operational amplifier portion and current offsets in the current mirror portion of the Bandgap circuit. When used together, the chopped stabilization and dynamic current matching techniques provide a significant increase in accuracy, especially when using small, low voltage devices in the analog blocks to reduce layout area and support low power supply operation (e.g., power supply values down to about 1.4 volts and below).
摘要翻译：本文描述了带隙参考（BGR）电路和方法，用于在BGR电路的模拟模块中使用小的低电压器件时提供高精度，低功率的带隙操作。在一些情况下，可以组合斩波输入稳定和动态电流匹配技术来补偿运算放大器部分中的输入电压偏移和带隙电路的电流镜部分中的电流偏移。当一起使用时，切断的稳定和动态电流匹配技术可以显着提高精度，特别是在模拟模块中使用小型低电压器件时，可以减少布局面积并支持低电源运行（例如，电源值低至约 1.4伏及以下）。

4. 发明申请

WO2005099088A1 INTEGRATED CIRCUIT HAVING ONE OR MORE CONDUCTIVE DEVICES FORMED OVER A SAW AND/OR MEMS DEVICE 审中-公开
标题翻译：具有通过SAW和/或MEMS器件形成的一个或多个导电器件的集成电路
公开(公告)号：WO2005099088A1
公开(公告)日：2005-10-20
申请号：PCT/US2005/009887
申请日：2005-03-24
申请人： CYPRESS SEMICONDUCTOR CORP. , FIELD, Dean, L. , STONE, Charles, N. , BRUNER, Michael, W.
发明人： FIELD, Dean, L. , STONE, Charles, N. , BRUNER, Michael, W.
IPC分类号： H03H9/05
CPC分类号： H03H9/0547 , H03H3/0073 , H03H3/08 , H03H9/0085 , H03H9/1057 , H03H9/1064 , H03H9/1092 , H03H9/14588
摘要： An integrated circuit is provided which includes one or more device elements (24) formed above a base substrate (22), a structure (43) forming a sealed cavity (46) above at least a portion of the one or more device elements (24), and one or more conductive devices (52) formed above the sealed cavity (46). A method for fabrication of such an integrated circuit is also provided. An exemplary embodiment of the integrated circuit includes a surface acoustic wave device having a plurality of tracks each with a first interdigitated transducer configured to convert a receiving electric field energy into mechanical wave energy and a second interdigitated transducer configured to convert the mechanical wave energy into an output electric field energy. The SAW device also includes a conductor arranged above and spanning across at least two tracks of the plurality of tracks and coupled to the first interdigitated transducers of at least the two tracks.
摘要翻译：提供一种集成电路，其包括形成在基底基板（22）上方的一个或多个器件元件（24），在所述一个或多个器件元件（24）的至少一部分上方形成密封空腔（46）的结构）和形成在密封空腔（46）上方的一个或多个导电装置（52）。还提供了这种集成电路的制造方法。集成电路的示例性实施例包括具有多个轨道的表面声波装置，每个轨道具有构造成将接收电场能量转换为机械波能的第一交叉换能器，以及配置成将机械波能量转换为输出电场能量。 SAW器件还包括布置在多个轨道中的至少两个轨道上方并跨越至少两个轨道的第一交叉换能器的导体。

5. 发明申请

WO2005002047A1 PHASE-LOCKED LOOP AND DELAY-LOCKED LOOP INCLUDING DIFFERENTIAL DELAY CELLS HAVING DIFFERENTIAL CONTROL INPUTS 审中-公开
标题翻译：相位锁定环和延迟锁定环，包括具有差分控制输入的差分延迟电池
公开(公告)号：WO2005002047A1
公开(公告)日：2005-01-06
申请号：PCT/US2004/021035
申请日：2004-06-25
申请人： CYPRESS SEMICONDUCTOR CORP. , BAKER, Michael, P. , MEYERS, Steven, C.
发明人： BAKER, Michael, P. , MEYERS, Steven, C.
IPC分类号： H03F3/45
CPC分类号： H03L7/0995 , H03F2203/45362 , H03F2203/45466 , H03F2203/45644 , H03K5/133 , H03K2005/00026 , H03K2005/00208 , H03L7/0812
摘要： A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.
摘要翻译：本文提供了一种差分延迟单元，其不仅接收一对差分输入值，而且还接收一对差分控制值，用于延迟差分输入值以产生一对差分输出值。因此，提供了一种真正差分的延迟单元，因此能够显着地提高噪声性能。本发明的差分延迟单元还表现出围绕中心频率，恒定增益和增加的调谐范围能力的高频稳定性。以这种方式，差分延迟单元可以分别用在PLL或DLL设计中，作为低噪声VCO或低噪声延迟线的一部分。

6. 发明申请

WO2004114611A2 ARCHITECTURE FOR NETWORK SEARCH ENGINES WITH FIXED LATENCY, HIGH CAPACITY, AND HIGH THROUGHPUT 审中-公开
标题翻译：具有固定时间，高容量和高通量的网络搜索引擎的架构
公开(公告)号：WO2004114611A2
公开(公告)日：2004-12-29
申请号：PCT/US2004/018235
申请日：2004-06-04
申请人： CYPRESS SEMICONDUCTOR CORP. , VENKATACHARY, Srinivasan , GUPTA, Pankaj , RANGARAJAN, Anand
发明人： VENKATACHARY, Srinivasan , GUPTA, Pankaj , RANGARAJAN, Anand
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , Y10S707/99931 , Y10S707/99932 , Y10S707/99933
摘要： An improved architecture for a network search engine (NSE) is disclosed herein as including an interface manager, one or more levels of a splitting engine, an array of data processing units (DPUs), and a cascade block. A method for using the improved NSE architecture to form an efficient pointer entry database is also provided. As described herein, the improved NSE architecture simultaneously provides high speed, search throughput, update rate and capacity, coupled with low power and fixed latency searches for all search key widths.
摘要翻译：本文公开了一种用于网络搜索引擎（NSE）的改进的架构，其包括接口管理器，分割引擎的一个或多个级别，数据处理单元（DPU）阵列和级联块。还提供了一种使用改进的NSE架构来形成有效的指针条目数据库的方法。如本文所述，改进的NSE架构同时提供高速度，搜索吞吐量，更新速率和容量，以及针对所有搜索关键字宽度的低功率和固定延迟搜索。

7. 发明申请

WO2013039694A1 LIGHTING CONTROL SYSTEM 审中-公开
标题翻译：照明控制系统
公开(公告)号：WO2013039694A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/052774
申请日：2012-08-29
申请人： KETRA, INC. , KNAPP, David, J. , HO, Horace, C. , LEWIS, Jason
发明人： KNAPP, David, J. , HO, Horace, C. , LEWIS, Jason
IPC分类号： H05B37/02 , H04B10/11
CPC分类号： H04L12/43 , H04B10/116 , H04L12/282 , H04L12/40013 , H04L12/413 , H04L12/437 , H04L12/6418 , H04L12/66 , H04L2012/285 , H05B37/0245 , Y02B20/48
摘要： Intelligent illumination device are disclosed that use components in an LED light to perform one or more of a wide variety of desirable lighting functions for very low cost. The LEDs that produce light can be periodically turned off momentarily, for example, for a duration that the human eye cannot perceive, in order for the light to receive commands optically. The optically transmitted commands can be sent to the light, for example, using a remove control device. The illumination device can use the LEDs that are currently off to receive the data and then configure the light accordingly, or to measure light. Such light can be ambient light for a photosensor function, or light from other LEDs in the illumination device to adjust the color mix.
摘要翻译：公开了一种智能照明装置，其使用LED灯中的部件来以非常低的成本执行各种所需的照明功能中的一种或多种。产生光的LED可以被暂时地周期性地关闭，例如，在人眼不能察觉的持续时间内，以使光以光学方式接收命令。光传输的命令可以被发送到光，例如，使用移除控制装置。照明装置可以使用当前关闭的LED来接收数据，然后相应地配置光，或者测量光。这种光可以是用于光传感器功能的环境光，或照明装置中来自其它LED的光，以调整颜色混合。

8. 发明申请

WO2008076737A2 MEMORY INTERFACE CONFIGURABLE FOR ASYNCHRONOUS AND SYNCHRONOUS OPERATION AND FOR ACCESSING STORAGE FROM ANY CLOCK DOMAIN 审中-公开
标题翻译：用于非同步和同步操作和从任何时钟域访问存储的记忆接口
公开(公告)号：WO2008076737A2
公开(公告)日：2008-06-26
申请号：PCT/US2007/087179
申请日：2007-12-12
申请人： CYPRESS SEMICONDUCTOR CORP. , KHODABANDEHLOU, Hamid , RAZA, Syed, Babar
发明人： KHODABANDEHLOU, Hamid , RAZA, Syed, Babar
IPC分类号： G11C7/10
CPC分类号： B21C23/085 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C11/40615
摘要： An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.
摘要翻译：提供了一种改进的存储器接口电路，用于以包括同步模式和异步模式的两种可用模式之一访问存储阵列。改进的存储器接口电路还包括逻辑，其使得存储阵列能够驻留在基本上任何时钟域内。

9. 发明申请

WO2007098445A1 INTERNALLY DERIVED ADDRESS GENERATION SYSTEM AND METHOD FOR BURST LOADING OF A SYNCHRONOUS MEMORY 审中-公开
标题翻译：内部地址生成系统和同步存储器的BURST加载方法
公开(公告)号：WO2007098445A1
公开(公告)日：2007-08-30
申请号：PCT/US2007/062433
申请日：2007-02-20
申请人： CYPRESS SEMICONDUCTOR CORP. , REZEANU, Stefan-Cristian
发明人： REZEANU, Stefan-Cristian
IPC分类号： G11C8/04 , G11C7/10
CPC分类号： G11C7/1027 , G11C8/04
摘要： An address generation system and method is provided for internally storing and thereafter producing an address to be sent to a memory device. The address that is stored need not be sent from an external address bus at each clock cycle, but the processing can remain internal to the memory device. The burst-block starting address can be stored in the mirror register (52) and output from a selector circuit, such as a multiplexer (54) when that address is chosen. Otherwise, the multiplexer can simply perform its normal operation of selecting between an address pointed to by a counter (60), the external address (ADDR, IN), or the incremented counter output, based on the state of the external counter control signals. The system includes a mirror register, a counter, and a multiplexer that selects either the mirror register stored address or the internally processed address.
摘要翻译：提供地址生成系统和方法，用于内部存储并且随后产生要发送到存储器设备的地址。存储的地址不需要在每个时钟周期从外部地址总线发送，但处理可以保留在存储器件的内部。当选择该地址时，突发块起始地址可存储在镜像寄存器（52）中，并从诸如多路复用器（54）的选择器电路输出。否则，多路复用器可以基于外部计数器控制信号的状态简单地执行其在计数器（60）指向的地址，外部地址（ADDR，IN）或递增计数器输出之间的选择的正常操作。该系统包括镜像寄存器，计数器和多路复用器，其选择镜像寄存器存储的地址或内部处理的地址。

10. 发明申请

WO2007098412A1 SYSTEM AND METHOD FOR TRANSFERRING DIFFERENT TYPES OF STREAMING AND PACKETIZED DATA ACROSS AN ETHERNET TRANSMISSION LINE USING A FRAME AND PACKET STRUCTURE DEMARCATED WITH ETHERNET CODING VIOLATIONS 审中-公开
标题翻译：用于通过使用以太网编码突破的框架和分组结构通过以太网传输线传输不同类型的流动和封装数据的系统和方法
公开(公告)号：WO2007098412A1
公开(公告)日：2007-08-30
申请号：PCT/US2007/062328
申请日：2007-02-16
申请人： STANDARD MICROSYSTEMS CORPORATION , KNAPP, David, J. , MUELLER, Rainer, P. , HO, Horace, C. , HECK, Patrick , KLOS, Rainer , THIEL, Christian
发明人： KNAPP, David, J. , MUELLER, Rainer, P. , HO, Horace, C. , HECK, Patrick , KLOS, Rainer , THIEL, Christian
IPC分类号： H04L12/64 , H04J3/06
CPC分类号： H04J3/0605 , H04J3/0647 , H04J3/0658 , H04J3/1605 , H04L12/40006 , H04L12/413 , H04L12/42 , H04L25/4908
摘要： A communication system, network, interface, and port architecture are provided for transporting different types of data across a network. The network can be arranged by connecting the ports in a daisy-chain fashion to achieve a ring architecture or topology. The network forwards data according to a specific network protocol, and nodes among the network can use a recovered clock from the bitstream to drive the transmitter and create a synchronous network even thought the network can receive Ethernet packets which are typically targeted for an asynchronous network. Non-compliant data, such as Ethernet data, can be sent as packets within a frame structure. The frame is synchronized to Ethernet coding violations used to signal the beginning of each frame, and each packet can be immediately followed by a packet coding violation. The frame and packet coding violations are represented as a sequence of 4B/5B codes that are not valid codes and, therefore, not present as Ethernet encoded data.
摘要翻译：提供通信系统，网络，接口和端口架构，用于通过网络传输不同类型的数据。可以通过以菊花链方式连接端口来实现网络，以实现环形架构或拓扑。网络根据特定网络协议转发数据，网络中的节点可以使用来自比特流的恢复时钟来驱动发射机，并创建一个同步网络，甚至认为网络可以接收通常针对异步网络的以太网分组。诸如以太网数据之类的不合规数据可以作为帧结构内的分组发送。帧被同步到以太网编码违例，用于发信号通知每帧的开始，并且每个数据包可能紧随其后的是一个数据包编码违规。帧和分组编码违例被表示为不是有效代码的4B / 5B代码序列，因此不作为以太网编码数据出现。

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