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1. 发明申请

WO2004017160A2 METHOD AND SYSTEM FOR ISSUING AND USING GAMING MACHINE RECEIPTS 审中-公开
标题翻译：用于发布和使用游戏机收据的方法和系统
公开(公告)号：WO2004017160A2
公开(公告)日：2004-02-26
申请号：PCT/US2003/023166
申请日：2003-07-25
申请人： IGT
发明人： ROWE, Rick , CHILTON, Ward
IPC分类号： G06F
CPC分类号： G07G5/00 , G06Q30/0209 , G06Q30/0212 , G06Q30/0225 , G07F17/32 , G07F17/3244 , G07F17/3248 , G07F17/3255 , G07F17/42
摘要： The invention comprises a gaming system including at least one gaming machine arranged to accept and print receipts. In one embodiment of a method, a player playing a gaming machine is issued a receipt which represents credit or value belonging to the player, and includes secondary information. The secondary information may comprise promotional award information, such as a matching bet for use in playing another game or a prize, or information unrelated to the games, such as a horoscope. In another embodiment of the invention, a method comprises issuing a first receipt at a first location, such as a parking garage, accepting the first receipt at a gaming machine, issuing a second receipt at the gaming machine and then accepting the second receipt at another location, such as a parking garage exit. In this method, the gaming machine serves as a validation mechanism to a player activity or event.
摘要翻译：本发明包括一个游戏系统，该游戏系统包括至少一个安排来接受和打印收据的游戏机。在方法的一个实施例中，玩游戏机的玩家被发出代表属于玩家的信用或价值的收据，并且包括次要信息。辅助信息可以包括促销奖励信息，诸如用于玩另一游戏或奖励的匹配投注或者与游戏无关的信息，诸如星座。在本发明的另一个实施例中，一种方法包括：在诸如停车库的第一位置处发行第一收据，在游戏机处接受第一收据，在游戏机处发行第二收据，然后在另一收据处接收第二收据位置，如停车场出口。在这种方法中，游戏机作为玩家活动或事件的验证机制。

2. 发明申请

WO2004025655A3 DYNAMIC NV-RAM 审中-公开
公开(公告)号：WO2004025655A3
公开(公告)日：2004-03-25
申请号：PCT/US2003/028748
申请日：2003-09-11
申请人： IGT
发明人： NELSON, Dwayne, R.
IPC分类号： G06F12/00
摘要： A method and apparatus of dynamically storing critical data of a gaming machine by allocating and deallocating memory space in a gaming machine is disclosed. One or more embodiments describe downloading or removing a new game to a gaming machine such that all existing critical data in NV-RAM memory is left intact. In one embodiment, the invention discloses a method and apparatus for dynamically allocating and deallocating memory space to accommodate either permanent or temporary storage in an NV-RAM. A method and apparatus is provided to monitor available memory space and dynamically resize the memory in NV-RAM. In one embodiment, a method is disclosed for performing an integrity check of the NV-RAM and determining whether a critical data error has occurred. In one or more embodiments, methods of compacting and shifting contents of an NV-RAM are described to consolidate available memory space or to prevent unauthorized access of NV-RAM memory.

3. 发明授权

US07239669B2 Asynchronous system-on-a-chip interconnect 有权
标题翻译：异步片上系统互连
公开(公告)号：US07239669B2
公开(公告)日：2007-07-03
申请号：US10634597
申请日：2003-08-04
申请人： Uri Cummings , Andrew Lines
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04L27/04
CPC分类号： G06F13/423 , G06F1/12 , G06F2213/0038 , H04L7/005 , H04L7/02 , H04L49/101 , H04L2012/5674 , H04Q3/0004 , H04Q2213/13034 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/13361 , H04Q2213/13362
摘要： Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
摘要翻译：描述了涉及包括多个同步模块的片上系统的方法和装置，每个同步模块具有由数据速率表征的相关联的时钟域，数据速率包括多个不同的数据速率。片上系统还包括多个时钟域转换器。每个时钟域转换器被耦合到对应的一个同步模块，并且可操作以在对应的同步模块的时钟域和根据异步握手协议的数据传输特征的异步域之间转换数据。异步交叉开关耦合到多个时钟域转换器，并且可在异步域中操作以实现任何两个时钟域转换器之间的先进先出（FIFO）通道，从而促进任何两个时钟域转换器之间的通信同步模块。

4. 发明授权

US07224566B2 Interfaces between semiconductor circuitry and transpinnor-based circuitry 有权
标题翻译：半导体电路和基于透明元件的电路之间的接口
公开(公告)号：US07224566B2
公开(公告)日：2007-05-29
申请号：US10419282
申请日：2003-04-17
申请人： David Green Baskin, legal representative , Stephen J. Nuspl , Richard Spitzer , E. James Torok , Edward Wuori
发明人： Arpad Barna, deceased
IPC分类号： H01H47/00
CPC分类号： G11C11/15 , G11C11/16 , H03K19/0175
摘要： Electronic systems are described including semiconductor circuitry characterized by first signals and all-metal circuitry characterized by second signals and comprising a plurality of transpinnors. Each transpinnor includes a network of thin-film elements. At least one thin-film element in each transpinnor exhibits giant magnetoresistance. Each transpinnor includes a conductor inductively coupled to the at least one thin-film element for controlling operation of the transpinnor. Interface circuitry connects the semiconductor circuitry to the all-metal circuitry and converts between the first signals and the second signals.
摘要翻译：描述了电子系统，其包括由第一信号和全金属电路表征的半导体电路，其特征在于第二信号并且包括多个透明元件。每个透明元件包括薄膜元件网络。每个透明体中至少有一个薄膜元件表现出巨大的磁阻。每个透明元件包括感应耦合到至少一个薄膜元件的导体，用于控制透明元件的操作。接口电路将半导体电路连接到全金属电路，并在第一信号和第二信号之间进行转换。

6. 发明授权

US07208389B1 Method of porogen removal from porous low-k films using UV radiation 失效
标题翻译：使用紫外线辐射从多孔低k膜去除致孔剂的方法
公开(公告)号：US07208389B1
公开(公告)日：2007-04-24
申请号：US10672311
申请日：2003-09-26
申请人： Adrianne K. Tipton , Brian G. Lu , Patrick A. Van Cleemput , Michelle T. Schulberg , Qingguo Wu , Haiying Fu , Feng Wang
发明人： Adrianne K. Tipton , Brian G. Lu , Patrick A. Van Cleemput , Michelle T. Schulberg , Qingguo Wu , Haiying Fu , Feng Wang
IPC分类号： H01L21/76
CPC分类号： H01L21/31695 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02348
摘要： Methods of preparing a porous low-k dielectric material on a substrate are provided. The methods involve the use of ultraviolet radiation to react with and remove porogen from a porogen containing precursor film, leaving a porous low-k dielectric matrix. Methods using oxidative conditions and non-oxidative conditions are described. The methods described may be used to remove porogen from porogen-containing precursor films. The porogen may be a hydrocarbon such as a terpene (e.g., alpha-terpinene) or a norbornene (e.g., ENB). The resulting porous low-k dielectric matrix can then be annealed to remove water and remaining silanols capped to protect it from degradation by ambient conditions, which methods will also be described.
摘要翻译：提供了在衬底上制备多孔低k电介质材料的方法。这些方法涉及使用紫外线辐射与含致孔剂的前体膜反应并除去致孔剂，留下多孔的低k电介质基质。描述了使用氧化条件和非氧化条件的方法。所描述的方法可用于从含致孔剂的前体膜中除去致孔剂。致孔剂可以是烃，例如萜烯（例如α-萜品烯）或降冰片烯（例如ENB）。然后可以将得到的多孔低k电介质基体退火以除去水和封闭的剩余硅烷醇，以保护其免受环境条件的退化，这些方法也将被描述。

7. 发明授权

US07203799B1 Invalidation of instruction cache line during reset handling 有权
标题翻译：复位处理期间指令高速缓存线无效
公开(公告)号：US07203799B1
公开(公告)日：2007-04-10
申请号：US10815559
申请日：2004-03-31
申请人： James Loran Ball
发明人： James Loran Ball
IPC分类号： G06F12/12
CPC分类号： G06F12/0891
摘要： Methods and apparatus are provided for handling events such as faults and resets. Specialized circuitry or hardware is provided within a processor to invalidate the cache line associated with the processor cache reset address. Based on the invalided state of the cache reset address line, the processor obtains new instructions from data memory. The new instructions can be configured to invalidate the remaining cache lines using software mechanisms.
摘要翻译：提供了用于处理故障和复位等事件的方法和装置。在处理器内提供专用电路或硬件以使与处理器高速缓存复位地址相关联的高速缓存线无效。基于高速缓存复位地址线的无效状态，处理器从数据存储器获取新的指令。新指令可以配置为使用软件机制使剩余的高速缓存行无效。

9. 外观设计

USD537126S1 Informational display assembly for a gaming table 有权
标题翻译：用于游戏桌的信息显示组件
公开(公告)号：USD537126S1
公开(公告)日：2007-02-20
申请号：US29238107
申请日：2005-09-09
申请人： Scott Boyd , Kevan Wilkins , Rick Rowe
设计人： Scott Boyd , Kevan Wilkins , Rick Rowe

10. 发明授权

US07179661B1 Chemical mechanical polishing test structures and methods for inspecting the same 有权
标题翻译：化学机械抛光试验结构及检验方法
公开(公告)号：US07179661B1
公开(公告)日：2007-02-20
申请号：US09648095
申请日：2000-08-25
申请人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
发明人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
IPC分类号： H01L21/00
CPC分类号： H01L22/34
摘要： Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
摘要翻译：公开了一种具有多个虚拟填料的半导体管芯，其中所述多个虚拟填料的位置和尺寸被设计成使化学机械抛光期间的缺陷最小化。虚拟填充物中的至少一个耦合到底层测试结构。在优选实施例中，半导体管芯还包括多个导电层和衬底。下面的测试结构包括由多个导电层中的第一个形成的第一层部分和将第一层部分连接到至少一个虚拟填充物的通孔。在另一方面，基础测试结构还具有将第一层部分耦合到衬底的通孔，并且底层测试结构包括多个层部分和通孔以形成多层测试结构。

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